Um, you might want to take a look at a labeled K8 die photo before you embarrass yourself further.
You mean the annotated version of Wouter's photo on Ace's?
You have got to be joking. Compare the 90 nm and 65 nm die photos. Notice the subtle differences in the small memory arrays between the instruction pipeline and the datapath side of the core.
You're clearly not looking very closely. It's *much* larger relative to the ALU, compared to the K8.
Maybe to the untrained eyes of someone who is hoping to see something that is not there.
Yet another garbage post from you.
You really think the 65 nm K8's L2 is implemented with 8 rough "row elements"?
These are the micro-code ep(roms) for complex cisc instructions. They operate as one single memory since they all get the same address from the micro-sequencer which handles the complex instructions. Going from 3 to 4 therefor doesn't say anything at all, it's just more memory, or the same amount of memory with larger cells. The rest of the architecture is visibly 3-way. The re- order buffer, the integer schedulers, the integer ALU's. "
The supposed FP boosted K8L with essentially unchanged FPU.
You're clearly not looking very closely. It's *much* larger relative to the ALU, compared to the K8.
Another nice call Doug.
">And what do you think about the floating point units? >
It's virtualy identical to existing K8's. There are also 3 HT units and not 4 as claimed by somebody at aces. It's not a K8L."
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