Advanced Micro Devices Inc (AMD)

[burn2learn]

yield loss is looked at by how many die per wafer is lost.

for an agressive process (or product)
1. LE (poly targeting losses to get speed) can be >50%
2. defects ~ 10-15%
3. excursions depends how bad and how long until contained

for non agressive

1. defects
2. excursions
3. Le loss

there is usually little loss between sort and assembly.at assembly most of the package can be tested independantly before combining with the chip. This changes radically based on package type which is driven by size and TDP. the amount of metal layers would add to the defect loss...maybe 5-10 die per extra metal layer, no additional le loss, and more risk to excursion.