Wednesday, June 18, 2003 11:33:22 PM
Didn't I see you already do that, and come up with a cost of about $25 per chip? Even that estimate used a defect density such that more than half the silicon would be thrown away.
Nope. I showed how it would yield on bulk silicon, not SOI. And as for the yield loss, that's what happens when you have a big die. Use the same defect density with a smaller die and you'll see the yield goes up in terms of percentage.
How so you know that AMD won't get much higher yields? They have been working on it, you know:
I suppose it's always possible for AMD to all of a sudden take a problematic process technology (SOI) and have far and away better yields than anyone else in the world does on a much less troublesome technology, bulk SI, but I wouldn't bet on it.
"Advanced Micro Devices Inc. (AMD) has developed a technology called Advanced Process Control (APC) that allows chipmakers to make fine adjustments to their tool sets while wafers go through the manufacturing process. AMD claims its homegrown technology is unmatched."
Please... You want me to start listing all the things AMD claimed that didn't come true?
Maybe there are many people in Dresden who can get the defect density down:
Maybe. Let's hope so.
Do you really think that the best yields AMD can expect are less than 50%?
The bigger the die the lower the yield in percentage. It's not an AMD thing. If you had 100 die on a wafer and 50 defects you'd see about 50% yield. If you had 200 die on the same wafer and the same 50 defects you'd see about 75% yield. Same process, same wafer, same defect density, different yield percentage. It's the big A64 die that makes the yield so low. A64 needs a huge cache to compete with Intel and this is the price they pay, so to speak. Big die, low yields and restricted capacity.
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