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SemiconEng

06/19/03 12:41 AM

#6703 RE: Elmer Phud #6701

"Advanced Micro Devices Inc. (AMD) has developed a technology called Advanced Process Control (APC) that allows chipmakers to make fine adjustments to their tool sets while wafers go through the manufacturing process. AMD claims its homegrown technology is unmatched."

Please... You want me to start listing all the things AMD claimed that didn't come true?



Actually APC has been around for quite some time, the year 1999 to be more precise. I have to say though that AMD's statement that "They developed it", and that it's a "Homegrown Technology", should result in those making those statements, to have their noses grow WAY beyond the dimension of Gepeto's wooden friend....

The technology was actually developed by a collaboration of Honeywell and AMD, with funding from Sematec, and was commercialized by Objectspace Fab solutions of Austin Texas in 1999-2000 timeframe. Honeywell at the time was a major manufacturer of control systems for the oil, and gas refining industry, which is probably where AMD gets their "We went outside the industry" (cough) claims.

As I understand it, Most of the benefits are realized in Lithography and Planer. In Litho, APC resulted in lower Litho Critical Dimension Sigma (Standard Deviation From The Mean), which decreased End Of Line Speed Sigma by 48%. The result for the initial systems in 1999 was an increase in End Of Line mean speed of +15MHz (Whoooo Hoooooo).

In Planer, where flatness of the polishing and Linear Material removal are the main objectives, it reduced the Cross Wafer Sigma by ~27%, which would most likely improve yields somewhat, although it's hard to tell how much, due to the effect of Planer Sigma being cumulative.

The biggest benefit most likely would not be in Speed increases, or Yield, but in Rework reduction. Initial reports were that due to the improvements in Litho, it had the "Potential" to reduce Litho rework by 83%. No matter how you slice it, that has to result in cost savings.

The main issue that I have with AMD's "announcement" of it now, is that the implementation was apparently accomplished in the 1999-2000 timeframe at AMD's fabs, so I would guess that APC is ALREADY factored into the CURRENT results from their Fabs. I wouldn't pin my hopes on any huge Future Speed and/or Cost benefits, since it seems to have been running in AMD's fabs for several years now, and was certainly operational during the entire development of Athlon and Opteron. Here are links if you want to read more......

http://www.nist.gov/public_affairs/factsheet/honeywell.htm
http://www.nist.gov/public_affairs/factsheet/honey2.htm

Semi
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ChrisC_R

06/19/03 12:43 AM

#6704 RE: Elmer Phud #6701

EP -

Re: "The bigger the die the lower the yield in percentage. It's not an AMD thing. If you had 100 die on a wafer and 50 defects you'd see about 50% yield."

Oh, so your analysis only considers simple wafer defect density - defects in the silicon crystal lattice. I thought your analysis addressed process defects too.

I was under the impression that wafer defects were a lot less significant these days, allowing for huge dies like the Itanium 2 (at 325 mm2) and beyond. But WTFDIK......

Still, I guess Intel isn't likely to be needing many Itaniums at the current rate of sales, so their yields don't matter.