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Re: Elmer Phud post# 6696

Wednesday, 06/18/2003 11:03:56 PM

Wednesday, June 18, 2003 11:03:56 PM

Post# of 97868
EP -

Regarding your: "How about you providing a yield estimate for a 193mm2 SOI die? Or just a defect density estimate and we can run the numbers ourselves. And while you're at it give us a cost estimate for a processed 200mm SOI wafer."

Didn't I see you already do that, and come up with a cost of about $25 per chip? Even that estimate used a defect density such that more than half the silicon would be thrown away.

How so you know that AMD won't get much higher yields? They have been working on it, you know:

"Advanced Micro Devices Inc. (AMD) has developed a technology called Advanced Process Control (APC) that allows chipmakers to make fine adjustments to their tool sets while wafers go through the manufacturing process. AMD claims its homegrown technology is unmatched."

http://www.e-insite.net/electronicnews/index.asp?layout=article&articleid=CA256661

Maybe there are many people in Dresden who can get the defect density down:

http://www.kla-tencor.com/news/pressroom/pdfs/lederer.pdf

Do you really think that the best yields AMD can expect are less than 50%?



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