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Nice article on IMEC. How they help accelerate mass commercialization, innovation, strategic shift away from China, and burgeoning AI demand. Nice that LWLG is woven in with IMEC who is a key R&D hub for tier 1 companies like Nvidia and Nokia.
Edit: And no to forget that LWLG dominates the data and telecom and Polymer sections of photonic roadmap
https://cepa.org/article/belgium-is-not-just-chocolate-and-beer-its-also-semiconductors/
"Key industry players such as Intel and Nvidia believe imec is crucial for their innovations and provide 75% of its funding. “Europe has two jewels,” Intel CEO Pat Gelsinger says. “One is ASML, the most advanced lithography, and the other is imec.”
Tkg, Critical. Defined as Indispensable, Vital. Sounds like an euphemism for UBIQUITOUS!
Interesting
https://www.advmf.com/advanced-micro-foundry-unveils-siphab-4-5-empowering-800g-1-6t-communication-with-next-generation-pdk/
SINGAPORE, March 26, 2024 – Advanced Micro Foundry (AMF), announces the launch of its latest Process Development Kit (PDK) – SiPhab 4.5. Combining AMF’s Silicon Photonics (Si Ph) technology leadership with the needs of high-speed data center interconnects, SiPhab 4.5 represents a leap in Silicon Photonics design.
In a bid to accelerate Si Ph adoption and improve development efficiency, AMF incorporates industry feedback, issuing bi-annual updates to its PDK. These updates include enhancements to the design of key devices such as high-speed modulators, photodetectors, micro-rings and couplers.
SiPhab 4.5 provides designers with a diverse array of high-speed devices, enabling the creation of 200G/lane designs for 800G and 1.6T applications. Among these devices, the latest 40GHz differential modulator stands out prominently. This version also introduces enhancements to bandwidth-enhanced SPP modulators, bi-directional monitor photodetectors, high-power photodetectors, multi-layer nitride edge couplers, and grating couplers tailored individually for O and C bands.
“With continuous improvements in our device portfolio, SiPhab 4.5 empowers designers to tackle new challenges in the Telecom, LiDAR, and Datacom sectors” stated Dr. Patrick Lo, Chief Technology Officer at AMF.
AMF’s CEO, Mr. Jagadish CV shared “More and more customers are adopting our PDK for new tape outs. We are committed to making AMF the premier technology and manufacturing choice to address evolving market needs in connectivity, computing and sensing.”
The new release also brings upgrades for LiDAR designers, featuring advanced editions of 2D Optical Phased Array and Coherent receivers. SiPhab 4.5 is interoperable with leading Electronic Design Automation (EDA) tools and is readily available for distribution to AMF’s customers.
The devices within SiPhab 4.5 are equipped with foundry statistical process control (SPC), reliability validation, streamlining qualification process for designers. This assurance of consistency and dependability ensures smoother deployment of AMF’s Silicon Photonics solutions.
For further details on PDK devices and specifications, reach out to AMF’s sales team at sales@advmf.com.
Vein, if you are an investor (owner) of LWLG and do not read the SEC filings, then I have no words.
We should have a 10Q to read tonight and over the weekend based on 1Q23 filing date (5/10). I will be analyzing the burn rate, legal and R&D expenses, and dissecting management commentary and any changes from recent 10K. Should keep us all occupied until Monday.
Pickle
Quite an elitist comment. When can the peasants speak?
Spartex
You got it. Your posts to shorts are hilarious BTW. SHM and meeting Lebby is definitely on my bucket list but my youngest son's birthday is May 26th so I stream it. Hoping future SHM dates give me more wiggle room. My wife also has a cousin in Castle Rock we need to go see. Assuming Lebby has already sent LWLG to the moon by SHM, I would like to ask him if he was tempted to cameo as Professor Xavier in the next Deadpool Wolverine movie. His expression would be priceless.
We focus on LWLG efforts, but should not forget these foundry partners have also invested considerable resouces working with LWLG, and that is for only one reason.
Dude,
I will preface this by saying I have never met Lebby or talked with him in person. I believe your questions on if/when LWLG should be sold, establish industry partnership(s), or go-it alone are the same questions the BOD and Lebby grapple with. I will attest based on my own experience that the vendor/supplier oversight of LWLG by its customers is/will be rigorous given its importance in the supply chain and how it is intertwined within the ecosystem. Crawling up every orifice of your organization's body so customers have complete assurances as to your management capabilities, product, financial stability, operating performance, corporate strategies, meet their continuity of business policy, is a standard course. That being said, LWLG is better prepared as a publicly-traded company to meet these demands given it allows a multitude of interested companies to access their SEC filings. LWLG files one document for all to see without have to dedicate resources to delivering a multitude of one-off requests with varying requirements. I think this may be one of the reasons LWLG beefed up the 2023 10K and will be more transparent with news events moving forward. Being publicly-traded on NASDAQ with audited financials and management infrastructure to meet SEC requirements is a big deal as is the quality of senior management, CEO and BOD. Credibility is priceless. I also believe the recent senior accountant hirings, purchasing manager, etc. were for future order ramp-up, but also could be to beef up the vendor management requirements these large foundries require. I have no idea what financial parameters these foundries have, but they know the burn rate and have some level of financial projections under NDA and that LWLG is a CAPEX-lite business with a very low break-even rate. This is elementary stuff for CFOs of GF, Nvidia, Broadcom, Amazon, Intel, etc. I also think OLED BOD influence helps set a framework here with some foundry discussions likely to include shared R&D expense, IP ownership, etc.
In the end it is all about control and how badly the industry giants want it. They can utilize contracts and vendor management to stay inside LWLG and wield control based on agreed upon contract terms, or next level, they can inject capital by purchasing a minority stake to financially solidify their investment, provide option to buy fully at some point, and gain board seats. Next level up, they could buy the entire company and own the goose that laid the golden egg. Nvidia is not waiting around per link below. If LWLG is indeed going to be woven into the fabric of this data ecosystem, then very exciting times ahead for all of us shareholders.
Nvidia pursues $30 billion custom chip opportunity with new unit
https://www.reuters.com/technology/nvidia-chases-30-billion-custom-chip-market-with-new-unit-sources-2024-02-09/
Why would the largest global conference and exhibition for optical communications ask Michael Lebby to be front and center? He was hand picked by industry giants and his fellow peers so he could fall flat on his face, maybe talk about the good old days when Dirty Harry kept San Francisco safe and you could walk around without shoe covers? That would be like making Homer Simpson the keynote speaker for Mensa. No, OFC is a visionary endeavor to discuss where technology needs to go so the world of data can move forward. Michael has something valuable to say about something remarkable that LWLG has accomplished and people in the industry and running these companies need to know about it now. Why now, because it is happening!
Well, the 10K is out, the quiet period is over, and the CEO just announced today that the communication strategy is going to throttled up in 2024 with important industry conferences on the horizon. Going to be tough for shorts to sleep from here on out.
2+2=4. "One of the metrics for successful implementation of PDK is to receive working modulator chips."
"In 2023 we worked with silicon-based foundry partners to help scale in volume our polymer modulator devices and we received working modulator chips from these foundries. We have advanced and matured our interactions with our foundry partners and we continue to receive working modulator chips for prototyping. Silicon-based foundries are large semiconductor fabrication plants developed for the electronics IC business, that are now engaging with silicon photonics to increase their wafer throughput. Partnering with silicon-based foundries not only demonstrates that our polymer technology can be transferred into standard production lines using standard equipment, it also allows us to efficiently utilize our capital. The foundry partnerships will allow us to scale our high-performance polymer optical engines quickly and efficiently. We have now received silicon wafers that range up to 200mm in diameter, which aligns well with foundry manufacturing."
Vein, I would recommend reading up on the economic principles of competitive advantage and barriers to entry. This is not where you put a ladder and some tools in the back of your truck and now you're a contractor. This is an immensely complex science that LWLG has perfected and protected with patents. This is why technology companies achieve hockey stick growth or get bought out. It is the only way for some companies to remain relevant as the technology rapidly evolves.
Micro, and it's an invasion!! Looks like the walls of Jericho may have fallen.
Pickle
F2,
Congrats on Vet school. My daughter graduates in May 2024 and just took her licensing exam. Couldn't be more proud of the woman she has become. Lebby continues to hammer home ubiquity inside a cocoon of NDAs. He is announcing the future. Paying off her vet school debt is on top of my list as well.
IMEC and SMART Photonics sign MOU
We are very pleased to announce that imec and SMART Photonics signed a Memorandum Of Understanding (MOU) to underpin their intention to work together in the field of hybrid integration of InP on SiN/SiPh.
This collaborative work will include topics like:
– Hybrid integration of InP on SiN/SiPh with Flip chip bonding and butt coupling
– Hybrid integration of InP on SiN/SiPh with micro-transfer printing
– Component design i.e. laser design and design of interface elements for the integration of InP/SiPh along with system demonstration and prototyping.
Via this cooperation IMEC and SMART Photonics intend to accelerate adoption and market pull of hybrid integrated solutions for domains such as datacom, automotive, agrifood and health
https://smartphotonics.nl/imec-and-smart-photonics-sign-memorandum-of-understanding/
Dude,
Do you know if Nokia might be using? Announced same time and tied to 6g which LWLG has been linked to.
https://www.nokia.com/networks/optical-networks/pse-6s/
With all of the NDAs and the white papers, the only hint Lebby can legally give us is "ubiquitous" over and over again. I'm embracing it.
Stockjumper
Yes that make sense. IMEC collaborates within the ecosystem and helps drive global industry standards based on the demands of the marketplace and technological innovation to arrive at developing scalable, cutting-edge technology solutions.
If IMEC is publicly saying that exotic EOPs (LWLG) are a necessity, then it has already been decided. EOPs will be an industry standard. Recent white papers demonstraing record breaking performance further support that assertion.
Tkg,
Yes, and a Ferrari plays nice music and is also exotic :)
Bumping back to top. This is from IMEC who is the global incubator/research and development arm for the chip industry that works with all of the largest foundries and throughout the photonic ecosystem. LWLG material is not optional, it is necessary, therefore, it will be ubiquitous.
Silicon Photonics Will Shine in the Age of AI
https://www.electronicdesign.com/technologies/embedded/article/21270649/electronic-design-silicon-photonics-will-shine-in-the-age-of-ai
For lane rates of 400 Gb/s, the SiPho toolbox needs a major upgrade. Especially on the transmission side, modulators with bandwidths of more than 100 GHz and sufficiently low optical losses are very hard to achieve in Si or Ge, which necessitates the introduction of “exotic” electro-optic materials.
Silicon Photonics Will Shine in the Age of AI
https://www.electronicdesign.com/technologies/embedded/article/21270649/electronic-design-silicon-photonics-will-shine-in-the-age-of-ai
Silicon photonics has become one of the key building blocks in the data center in recent years. It uses the power of photons to connect switches, servers, and other gear fast and efficiently over long distances.
But silicon photonics is bound to become more important as the demand for bandwidth continues to rise. Or that’s what the experts at imec, one of the world’s leading semiconductor research labs, will tell you.
For imec, it’s only a matter of time before silicon photonics starts taking responsibility for chip-to-chip connectivity between CPUs, GPUs, and other XPUs—where the “X” stands for any computer architecture that best suits the needs of a specific workload—at the heart of data centers and AI supercomputers.
Integrating optics and electronics so closely together is a huge challenge. But the semiconductor industry is rising to meet it. The rise of a new generation of switch chips with co-packaged optics is proof of that.
imec said it sees a path to improving the power efficiency (picojoules per bit), bandwidth density (Tb/s per mm), and cost (Gb/s per dollar) of silicon photonics by an order of magnitude over time. That would open the door to a more advanced form of co-packaged optics called “wafer-level optical interconnects,” which can transfer data between chips on a printed circuit board (PCB) or inside a package at the speed of light.
To learn more about the innovation happening behind the scenes, we sat down with Joris Van Campenhout, the director of imec’s Optical I/O program. This interview has been edited for clarity.
What innovations will be needed in coming years to keep up with the networks in data centers?
Over the last decade, the shift from 100G to 200G to 400G pluggable optics has enabled cloud data centers to support the ever-growing demand for everything from video streaming and web browsing to social networking and cloud computing, among other uses. Continuing this evolution, 800G pluggable modules will soon enter the field, and 1.6T optics are expected by 2026, connecting data-center switches through single-mode fiber cabling over distances spanning hundreds of meters of distance.
The need for speed in data centers is, on the one hand, being driven by the CMOS scaling of data center switches, and on the other hand, by evolving IEEE Ethernet transceiver (TxRx) standards.
Historically, the lowest-cost transceiver solutions have been obtained by minimizing the number of parallel optical channels or lanes. Therefore, the key is the baud rate (or signaling rate) of the optical transceiver, which refers to the number of symbols that can be transmitted per second through a single optical channel.
The first generation of 1.6-Tb/s pluggable optics will be implemented with eight parallel lanes, each carrying 200 Gb/s, with baud rates scaling up to 100 Gbaud (Gbd) with PAM-4. For the subsequent generation running at 400 Gb/s per lane, baud rates will likely scale to 140 Gbd and modulation formats will grow even more complex.
This evolution drives the development of high-bandwidth electro-optical modulators and photodetectors. Insufficient bandwidth in the electro-optical channels degrades the quality of the data transmission. This must be mitigated with digital signal processors (DSPs), implemented on the most advanced CMOS nodes. But these DSPs add considerable power, latency, and cost. And so there is clear demand for optical components with bandwidths of more than 100 GHz that will substantially reduce the need for DSPs.
How is imec contributing to overcoming these challenges for data centers?
For years, imec has advanced the state of the art in silicon photonics and, more recently, we have worked out many silicon- and germanium-based electro-optical components at bandwidths of up to 50 GHz, enabling 200-Gb/s PAM-4 transmission in the first-generation of 1.6-Tb/s pluggable optics.
We are also overcoming a host of issues that prevented us from integrating lasers, waveguides, and other optical building blocks. We realized the integration of high-quality low-pressure chemical vapor deposition (LPCVD)-based SiN waveguides in imec’s SiPho platform—which was a challenge before due to the high temperatures required to create them. The heat can negatively impact the performance of Ge- and Si-based active electro-optic devices. It complements our toolbox with high-precision passive optical components.
Moreover, we developed SiPho interfaces for flip-chip-based laser integration, which will help reduce the overall transceiver cost. Lasers used in silicon photonics are not natively available in a CMOS production process. Using this process, we recently demoed indium-phosphide (InP) distributed-feedback (DFB) laser diodes bonded onto silicon-photonics wafers with an alignment precision within 300 nm and coupling loss less than 2 dB.
For lane rates of 400 Gb/s, the SiPho toolbox needs a major upgrade. Especially on the transmission side, modulators with bandwidths of more than 100 GHz and sufficiently low optical losses are very hard to achieve in Si or Ge, which necessitates the introduction of “exotic” electro-optic materials.
We are carrying out early integration pathfinding efforts aimed at the hybrid or heterogeneous integration of such non-CMOS materials in the SiPho process, exploring techniques such as micro-transfer printing.
In what other domains will we see high-bandwidth optical interconnect networks emerge?
The recent arrival of large generative AI models such as ChatGPT and Lambda has put a spotlight on the importance of networking bandwidth when using high-performance AI/ML clusters used to train such models. Pluggable optical interconnects have already started to replace copper (Cu) interconnects within such computer clusters, easing the bottlenecks between multi-XPU servers across distances of a few to tens of meters.
But as these clusters scale to thousands of XPUs, optical interconnects will gradually move into the board and package to meet high chip-to-chip interconnect bandwidth requirements. This evolution puts even more pressure on metrics like bandwidth density, cost, power, and reliability. Optical transceivers with more than a Tb/s per mm of bandwidth density, power consumption of less than 5 pJ/bit, link latency of less than 100 ns, and high reliability will be needed—all at a cost of 10 cents per Gb/s or less.
Unlike standard data-center networks, the tight power and latency budgets of AI/ML clusters leave no or very little room for digital signal processing. This means that the optical channels need to be very “clean,” with extremely low bit error rates (BERs).
In the context of AI and ML, how are you trying to address these problems with silicon photonics?
For these systems, a more appropriate way to scale bandwidth in these systems is by using a larger number of parallel optical channels, each running error-free at data rates in the range of 16 to 64 Gb/s, using optical and electrical components optimized for efficiency rather than bandwidth. In turn, aggressive wavelength division multiplexing (WDM) with 8, 16, or more wavelengths helps keep the total number of physical optical channels in check.
To connect optical I/O modules with the XPU or high-bandwidth memory (HBM), wafer-level co-packaged optics are emerging (see figure). For this technology, we want to leverage as much as possible emerging, advanced wafer-level 2.5D and 3D packaging technologies such as “micro” bumps, through-silicon vias (TSVs), silicon bridges, and eventually hybrid bonding.
Then, we leverage power-efficient electrical wide-I/O electrical interfaces for the “last-mile” copper interconnects. Finally, cost and optical link budgets are increasingly driving for integration of the light sources onto the SiPho chips.
imec
The diagram shows the differences between co-packaged optics and the “wafer-level" co-packaged optics in development.
For both cloud data centers and AI/ML clusters, networking bandwidth has become an increasingly important metric to determine system-level performance. The networking bottleneck is creating a serious sense of urgency, translating into strong engagements for silicon-photonics adoption by the industry.
Can you discuss any recent research highlights in the AI/ML context?
Recent research is focused on optimizing silicon ring modulators, WDM filters, and circuits for enabling low-power hybrid CMOS-SiPho transceivers. Ring-based WDM SiPho transceiver architectures have the potential to realize the performance metrics required for AI/ML clusters.
imec recently debuted a ring-based CMOS-SiPho transceiver with optical energy consumption as low as 3.5 pJ/bit and less than 10-12 BER, effectively “error-free.” The solution is scalable to 800 Gb/s per mm of bandwidth density, using eight wavelengths.
The move toward SiPho transceivers with a growing number of optical lanes comes with a higher risk of yield loss. This should be avoided as much as possible from a cost perspective. To measure and subsequently improve yield, we’re working on wafer-scale solutions for known-good die (KGD) testing of the SiPho transceivers.
Where are you taking silicon photonics next? What do you expect to achieve in the long term?
Wafer-level co-packaged optics combined with aggressive WDM is considered a viable approach to achieve 2- to 4-Tb/s/mm fiber-coupled optical links for AI and ML systems, with power consumption down to 1 to 2 pJ/bit. But by the end of the decade, we anticipate the need for optical interconnects approaching 10 Tb/s per mm of bandwidth density at power consumption well below 1 pJ per bit.
We recently started exploring wafer-level optical interconnects—our long-term vision for ultra-high-bandwidth chip-to-chip optical I/O. This deeply integrated optical I/O technology will ultimately enable massively parallel, optical XPU-to-XPU connectivity, promising tremendous gains in system performance.
There are other challenges that we’re trying to solve along the way. For instance, a key challenge is to deploy those scaled electrical interconnects and related process flows while enabling the optical fiber coupling interfaces. Today, fibers are "glued" to SiPho chips after actively aligning them to ensure good coupling efficiencies. In future implementations, it’s highly desirable to have "pluggable" fiber connectors, where the fibers are plugged into the package or the chip itself at the very last step.
imec has extensive in-house expertise. How does it positively impact your optics research?
Since the start of the Optical I/O program in 2010, imec has acquired a wealth of know-how when it comes to developing integrated silicon photonics, leveraging decades of CMOS integration knowledge.
Furthermore, advanced forms of co-packaged optics require cutting-edge 3D integration technologies, for which we can rely on the years of experience gained within imec’s 3D system integration program. In the same vein, our long-term vision to plug optical interconnects into wafer-level packaging needs to be supported by a system-level analysis, for which we are collaborating with imec’s system-technology co-optimization (STCO) team.
The unique availability of such diverse competencies under one roof—along with the strong presence of our partner ecosystem—helps foster the development of highly complex systems and technologies.
Yes, need to get those shares to these valuable employees before rocket launch. Closer and closer.
European consortium to develop next-generation silicon photonics
19 June 2023
My comment: Xfab is on Lightwave SHM slide 35 and Ligentec was there previously
A new European initiative has been launched with the aim of establishing an industrial value chain as well as photonics foundry and assembly capabilities for the development and high-volume production of next-generation silicon photonics.
Over the next 3.5 years, the partners of the “photonixFAB” consortium are looking to lower the barrier to accessing both low-loss silicon nitride (SiN) and silicon-on-insulator (SOI) based photonics platforms with indium phosphide (InP) and lithium niobate (LNO) heterogenous integration capabilities.
The initiative is designed to enable the European semiconductor and photonics industries to gain greater sovereignty, strengthening the continent’s manufacturing capabilities in key emerging areas.
X-FAB, a leading analogue/mixed-signal and specialty foundry, will lead the European consortium, which covers the main part of the silicon photonics value chain, from design automation via foundry service all the way to end users.
Other consortium members include: technology and manufacturing service providers Ligentec, Smart Photonics, Phix Photonics Assembly and Luceda Photonics; application developers Nokia, NVidia, Aryballe, Brolis Sensor Technology and PhotonFirst; as well as major research organisations CEA-Leti and imec.
A multitude of prospective opportunities for the cutting-edge photonic devices fabricated via photonixFAB have already been identified. Among them are data communication, telecoms, biomedical sensors/detectors, quantum computing and vehicle lidar.
Rudi De Winter, CEO of X-FAB says: “Seeing huge potential emerging there, traditional semiconductor vendors, OEMs and start-ups are all now exploring photonic-enabled applications. Consequently, this is the right time for companies to work together on building an extensive Europe-centric silicon photonics ecosystem that will help drive the continent’s competitiveness in this exciting new market.”
Thomas Hessler, CEO of Ligentec, adds: “Europe has a leading edge in the research of PICs. photonixFAB is the next necessary step to turn this technology lead into a world leading industry, contributing to the strategic autonomy of Europe.”
Ligentec will focus on the advancement of its low loss SiN PIC platform, recently installed at X-FAB and now commercially accessible as 200mm wafer technology. A key outcome of the project will be an improved offering for agile prototyping with a seamless transfer to volume production. Ligentec will also work within the consortium on the integration of lasers, high speed modulators and detectors, by adding III-V material based active devices and electro-optical materials such as LNO to the low loss SiN PIC platform.
Meanwhile, Luceda Photonics will look to establish mature process design kits (PDKs) and commence bringing European PIC technologies to manufacturing. The integration of a highly automated design flow will play a pivotal role in this value chain.
Pieter Dumon, Luceda Photonics’ CTO: “Considering the substantial investment required for the development and manufacturing of photonic integrated circuits (PICs), a reliable and automated design flow is of essential importance. Through this project, we aim to set a major step toward PIC design based on well-calibrated simulation models, seamlessly integrated with Luceda’s automated design flow, thus minimising errors and ensuring efficiency.”
The project is being supported by the Key Digital Technologies Joint Undertaking (KDT JU), with funding from EU and the national authorities. The combination of this funding and the investments being made by each of the consortium members totals €47.6m.
https://www.fibre-systems.com/news/european-consortium-develop-next-generation-silicon-photonics
Mdk, and as written in the CHIPS Act, the recognition phase.
WORK-BASED LEARNING.—The term ‘‘work-based learning’’ has the meaning given the term in section 3 of the Carl D. Perkins Career and Technical Education Act of 2006 (20 U.S.C. 2302).
18 (b) FINDINGS.—Congress finds that— (1) the coming end of Moore’s Law presents major technological challenges and opportunities for the United States and has important implications for national security, economic competitiveness, and scientific discovery; (2) future progress and innovation in microelectronics, and the maintenance of a robust domestic microelectronics supply chain, will require an approach that [[u]b]advances relevant materials science, electronics and [b]photonic device technologies, processing and packaging technologies, manufacturing technologies, circuit, chip, and system architecture, and software system and algorithm development in a codesign fashion;
https://www.commerce.senate.gov/services/files/CFC99CC6-CE84-4B1A-8BBF-8D2E84BD7965
US AIM Photonics launches new opto-electronic testing services
https://optics.org/news/14/5/34
30 May 2023
Expands access to client firms to advanced testing capabilities for prototypes.
AIM Photonics, the industry-driven research institute based in Albany, New York, has announced the launch of its new Opto-electronic Testing Services, which feature a full suite of advanced tools for testing both photonic integrated circuits (PICs) as well as conventional electronic ICs.
The new service will be offered through AIM's Test, Assembly and Packaging facility in Rochester, NY, which AIM says is the only place in the U.S. that provides access to both photonic and electronic test, assembly, and packaging prototyping services for substrates up to 300 mm wafers.
“Our comprehensive toolset can test and measure multiple performance aspects of electronic and photonic devices before and immediately after package assembly, allowing for rapid verification and optimization of the manufacturing process all in the same R&D center, saving our members and customers valuable time and resources,” said Chris Striemer, Business Development and Facilities Manager at AIM Photonics test, assembly and packaging facility.
AIM’s Opto-electronic Testing Services currently include over 30 tools for passive optical, active optoelectronic, telecom/datacom, and RF and DC testing. “Providing access to these services is core to our mission to expand the silicon photonics ecosystem,” Striemer
Multiple tools
“With this toolset, we are able offer a wide range of testing capabilities for on-wafer, die-level, and packaged devices, all aimed at achieving consistent and reliable results to support our members’ and customers’ prototype development.”
Striemer also said that the funds recently authorized through Empire State Development by the NYS Photonics Board will further expand AIM Photonics’ test and measurement capabilities over the next several years through additional hardware and partnerships with Rochester area colleges and universities.
“Our customers include not only small businesses, academics, and of course our government partners, but also research and development groups in companies—both large and small—that want to explore photonics without having to invest in testing infrastructure,” said Amit Dikshit, design enablement manager at AIM Photonics.
Purchasing advanced test and measurement tools can be cost-prohibitive for many companies, particularly start-ups with limited resources, Dikshit added. “Even basic test capability could cost several hundred thousand dollars and take up to a year to purchase, install and test,” he said.
“Having access to our extensive testing capabilities—as well as our finely-tuned methodologies—allows our members and customers to leave the testing to us, freeing them to focus their efforts on designing and developing their own innovative devices and technologies,” Dikshit said.
Forztnt2, thanks! Love it when we get the PR before the PR.
Marco, to your excellent point
https://www.datacenterfrontier.com/sustainability/article/11427134/water-restrictions-in-southwest-may-raise-the-bar-for-data-center-operators
Zero net carbon, ROI, speed, water use, AI, power are all creating a perfect storm for LWLG.
Sorry if posted previously. The future technology of datacentres. The technological evolution of the datacentre has been addressed by Imec’s Joris Van Campenhout.
https://www.electronicsweekly.com/news/business/the-future-technology-of-datacentres-2023-04/
“Over the past decade, the consecutive introduction of 100G, 200G and 400G pluggable optics has enabled cloud datacenters to support the ever-growing demand for a plethora of applications, such as video streaming, web browsing, social networking, cloud computing and many more,” says Van Campenhout, “continuing this evolution, 800G pluggable modules will soon enter the field and 1.6T optics are expected by 2026, interconnecting the datacenter switches through single-mode fiber cabling across hundred meters of distance.”
“The continued bandwidth increase in datacenter networking is on the one hand driven by the CMOS scaling of the datacenter switches, and on the other hand by the evolving IEEE Ethernet transceiver (TxRx) standards,” he continues, “historically, the lowest cost transceiver solutions have been obtained by minimizing the number of parallel optical channels or lanes. Therefore, the key scaling vector is the baud rate (or signaling rate) of the optical transceiver, which refers to the number of symbols that can be transmitted per second through a single optical channel. The first generation of 1.6T pluggable optics will be implemented with eight parallel lanes, each carrying 200 gigabits per second (Gbps), by scaling baud rates to 100 gigabaud (Gbd) combined with four-level pulse-amplitude modulation (PAM-4). For the subsequent generation running at 400Gbps per lane, baud rates will likely scale to 140Gbd and modulation formats will grow even more complex.”
“The key scaling vector is the baud rate (or signaling rate) of the optical transceiver, which refers to the number of symbols that can be transmitted per second through a single optical channel,” says Van Campenhout, “the evolution towards higher baud rates drives the development of high-bandwidth electro-optical modulators and photodetectors. Insufficient bandwidth of the electro-optical channels results in degraded data transmission quality. This needs to be mitigated with advanced digital signal processing (DSP), implemented in the most advanced CMOS nodes. But DSP adds considerable power, latency and cost. Therefore, there is a clear demand for optical components with bandwidths beyond 100GHz that would substantially reduce the need for DSP.”
“Over the past years, imec has advanced the state-of-the-art in Si photonics (SiPho) technology as part of the Optical I/O program. Many Si- and Ge-based electro-optical components have been demonstrated at 50GHz bandwidth, enabling 200Gbps PAM-4 transmission for the upcoming, first-generation 1.6T pluggable optics,” says Van Campenhou, “recently, we also realized the integration of high-quality low-pressure chemical vapor deposition (LPCVD)-based SiN waveguides in our SiPho platform, complementing our toolbox with high-precision passive optical components. Moreover, we developed the SiPho interfaces for flip-chip-based III-V laser integration, which will help to reduce overall transceiver cost. Using this process, we recently demonstrated indium-phosphide (InP) distributed-feedback (DFB) laser diodes bonded onto silicon photonics wafers with an alignment precision within 300nm and coupling loss less than 2dB.”
“For lane rates at 400Gbps, the SiPho toolbox needs a major upgrade,” he continues’ “Especially on the transmission side, modulators with bandwidth beyond 100GHz and sufficiently low optical losses are very hard to achieve in Si or Ge, which necessitates the introduction of “exotic” electro-optic materials such as LiNbO3, BaTiO3 or chromophore polymers. We are carrying out early integration pathfinding efforts aimed at the hybrid or heterogeneous integration of such non-CMOS materials in the SiPho process flow, e.g., exploring techniques such as microtransfer printing. In addition, IDLab, an imec research group at Ghent University, has recently demonstrated SiGe BiCMOS analog front-end electronics capable of driving the SiPho modulators and photodetectors at 200Gbps/lane.”
“The recent arrival of large, generative AI models such as ChatGPT, GPT-4 and Lambda has put a spotlight on the importance of sufficient networking bandwidth for high-performance AI/ML clusters, used for training such models,” adds says Van Campenhout, “pluggable optical interconnects have already started to replace Cu interconnects within such compute clusters, interconnecting the multi-XPU servers across distances of a few to tens of meters. As these clusters scale to thousands of XPUs, optical interconnects will gradually move into the board and package, to meet the high chip-to-chip interconnect bandwidth requirements. This evolution puts even more pressure on metrics like bandwidth density, cost, power, and reliability. Optical transceivers with multi-Tbps/mm bandwidth density, power consumption well below 5pJ/bit, low link latency (<100ns), and high reliability will be needed – all at a cost of 10c$/Gbps or less.”
”As AI/ML clusters will scale to thousands of XPUs, optical interconnects will gradually move into the board and package, to meet the high chip-to-chip interconnect bandwidth requirements,” says says Van Campenhout.
“Unlike for datacenter networks, the tight power and latency budgets leave no or very little room for digital signal processing,” he continues, “this means that the optical channels need to be very ‘clean’, with extremely low bit error rates. Therefore, for these systems, a more appropriate way to scale bandwidth is by using a larger number of parallel optical channels, each running error-free at modest data rates in the range of 16-64Gbps, using optical and electrical components optimized for efficiency rather than bandwidth. Aggressive wavelength division multiplexing (WDM) with 8, 16 or more wavelengths in turn helps to keep the total number of physical optical channels in check. To connect the optical I/O modules with the XPU or high bandwidth memory (HBM) stacks, wafer-level co-packaged optics is emerging, leveraging the power-efficient electrical wide-I/O electrical interfaces for the “last-mile” copper interconnects. Finally, cost and optical link budgets are increasingly driving for integration of the light sources onto the SiPho chips.”
Imec’s vision for wafer-level CPO (WL-CPO), with aggressive WDM scaling.
“For both cloud datacenters and AI/ML clusters, networking bandwidth has become an increasingly important metric determining system-level performance,” continues says Van Campenhout, “the networking bottleneck has created a high sense of urgency, translating into strong engagements for silicon photonics adoption by the industry.
“Recent research activities focus, among others, on optimizing silicon ring modulators, WDM filters and circuits for enabling low-power hybrid CMOS-SiPho transceivers. Ring-based WDM SiPho transceiver architectures show great potential to realize the performance metrics required for AI/ML cluster applications. At the 2023 Optical Networking and Communication Conference (OFC 2023), imec demonstrated an “error-free” (i.e., bit error rate <10-12) ring-based CMOS-SiPho transceiver with optical energy consumption as low as 3.5pJ/bit. The solution is scalable to 800Gbps/mm bandwidth density, using 8 wavelengths.”
”The move towards SiPho transceivers with a growing number of optical lanes comes with a higher risk of yield loss,” he adds, “this should be avoided as much as possible from a cost perspective. Therefore, to measure and subsequently improve yield, we are developing wafer-scale solutions for known-good die (KGD) testing of the SiPho transceivers.”
“Wafer-level co-packaged optics combined with aggressive WDM is considered a viable approach towards 2-4Tbps/mm fiber-coupled optical links for AI/ML system applications, with power consumption down to 1-2pJ/bit,” continues says Van Campenhout, “but, by the end of the decade, we anticipate the need for optical interconnects approaching 10Tbps/mm bandwidth density, at power consumption well below 1pJ/bit. We recently started pathfinding activities towards wafer-level optical interconnects, our long-term vision for ultrahigh-bandwidth chip-to-chip optical I/O. This deeply integrated optical I/O technology will ultimately enable massively parallel, optical XPU-to-XPU connectivity, promising tremendous gains in system performance.”
“By the end of the decade, we anticipate the need for optical interconnects approaching 10Tbps/mm bandwidth density, at power consumption well below 1pJ/bit,” he says m.
“Since the start of the Optical I/O program in 2010, imec has acquired a wealth of know-how in developing silicon integrated photonics, thereby leveraging decades of CMOS integration knowledge. Furthermore, advanced implementations of co-packaged optics require cutting-edge 3D integration technologies, for which we can rely on the years of experience gained within imec’s 3D system integration program. In the same realm, our long-term vision to introduce optical interconnects in the wafer-level package needs to be supported by a system-level analysis, for which we are collaborating with imec’s system-technology co-optimization (STCO) team. The unique availability of such diverse competences under one roof, together with the strong presence of our partner ecosystem, fosters the exchange of ideas and accelerates the development of highly complex systems and technologies.”
“Conversely, developments in the context of the optical I/O program feed other application-oriented integrated photonics activities pursued within imec – such as next-gen LiDAR, quantum cryptography, consumer health, medical diagnostics and agrifood – some of them in collaboration with partners from the Dutch PhotonDelta ecosystem, ” concludes Van Campenhout.
Let's have the headlines be how the shorts were crushed when LWLG entered commercialization full thottle rather than running to a lawyer. It is about displaying strength rather than weakness. If LWLG's lawyer confirms illegality then sends a private nasty gram threatening prosection, that is great but don't publicize it.
How about in Willy Wonka when Augustus is stuck in the tube with pressure building quickly!
"The suspense is terrible. I hope it’ll last."
I hear Donkey Kong.
Premature implies an unfair or inaccurate valuation which I would assume no shareholder would ever vote for. The point of my post specifically was whether the rapidly developing, colliding market and ecosystem dynamics could bring forward a fair company valuation sooner than we anticipated. Agree absent a fair valuation inclusive of future earnings, market ubiquity, LWLG would stay independent, driving the value higher.
Marco,
LWLG is at the center of an internet ecosystem that desperately needs an overhaul for deployment of the next generation of business and technology use cases. The ROI is already there but accelerants like AI (one of the most impressive slides from SHM), LIDAR, Data, zero net carbon, power, energy, etc. will only fuel more rapid adoption of the technology required for deployment and sustainable platforms. The hockey stick growth from AI, LIDAR, Data, Telecom, etc.) will, in turn, drive hockey stick growth for companies like LWLG who can build the architecture of the next generation platforms. While a number of us believe a buyout is inevitable, when that will occur just started the clock with LWLG's first licensing deal. Does rapid adoption and "pull" market demand create a near-term need for an acquirer to exert complete control over its technology roadmap, which is either dependent or impeded by LWLG's superior technology, by seeking a buyout sooner and for a higher amount to ensure its long term market relevance.
Pickle
Purely a guess. High growth companies demand a higher P/E. I reviewed NVIDIA a year ago or so to see if it was close. I would need to update again.
Thanks, I jumped the shark on that one.
KCCO,
Little adrenaline on a lazy Saturday. Quick math on $5B in revenue is $1.5B in net income (conservative 30% net margin estimate) with ~120M shares outstanding is $12.50 earnings per share. Assuming a 50 P/E equals $625/share. Wowza!
Ted, say it with me slowly and use your diaphragm.
C O M M E R C I A L I Z A T I O N !