Intel has no intention of having a duopoly.

And why would cpu buyers care what Intel intentions are ?

XD1 != XT3.
XD1 was previously know has Octigbay 12K, XT3 is production
version of Redstorm.

Indeed, thanks for the correction!

But yes you are correct, Cray could ofused more then 1 CPU per ASIC.

That is what I was trying to convey - 1:1 ratio of Opterons to ASICs is a choice, not a necessity as chipguy claimed.

isn't the Pathscale announcement of last week an indication that cheap fast switches are going to be commodities? ASICS (Application specific integrated chips) such as Cray's seem to be first cut solutions. More general answers to the problems of hooking together large arrays of processors are undoubtedly going to appear sooner rather than later.

Pathscale announcement addressed cheaper systems with higher latencies. ASICs are the best from the performance point of view, however, they are also more expensive.

Chipguy appears to be fixated on the ASIC count alone, while ignoring other considerations.

Yeah why worry about a ~$2000 ASIC when it
connects to a $300 processor. :-P

Do you actually have solid info on this ~$2k cost to Cray, or are you just guessing?

Again, ASIC is a fully in-house intermediate product for Cray. The Red Storm contract alone must have paid for the ASIC's R&D. The incremental cost of manufacturing itself should be reasonable, at most around few hundred dollars. Opterons, on the other hand, have to be purchased at the list price.

Repeat after me, Cray is selling COMPLETED systems, and their profits are the revenues minus the cost. Under such conditions, only the ASIC's incremental cost figures into the equation, and not some made up "list" price that the ASIC would have cost if bought outside from a company trying to recoup the R&D costs and make some profit.

To save time and money, Red Storm is not using symmetric multiprocessing features built into the Opteron. However, Alverson said he expects Cray to create systems based on four- or eight-way SMP nodes for future customers.

Yep. The system they are selling now (Cray XD1) has 12 cpus per module. In the module, every pair of cpus talks to each other. In addition, each cpu talks to its own ASIC chip. They could have easily used 1 ASIC per 2 cpus, just like in regular dual machines. The key here is that Hypertransport allows lots of flexibility depending on what is required.

http://www.cray.com/downloads/Cray_XD1_Datasheet.pdf

In Itanium machines, each ASIC must handle both the inter-cpu traffic, and the DRAM accesses over the same bus. When there are 2 cpus on a bus, the bandwidth is shared by many things.

Chipguy appears to be fixated on the ASIC count alone, while ignoring other considerations.

Then why did Cray link *each* Opteron in Red Storm
directly to a companion great mother of an ASIC that does
all system level routing and interconnect? 10K Opterons and
10k expensive ASICs. The 10k I2's in SGI's Columbia talk to
5k SHUB ASICs.

Sure! 2 Itaniums use the same proprietary bus to talk to each other, and talk to the other Itaniums in the system. That certainly should have HUGE positive effect on the performance! And do not forget to redesign the ASIC once the bus changes. Seriously, though, are you actually portraying a shortcoming as an advantage?

On the other hand, a Hypertransport link to an ASIC is quite straightforward in terms of the design, and such an ASIC can be easily recycled for other purposes in the system. And, with 10k cpus there are no other options than to have custom routing of the data traffic.

Also, remember, the majority of the ASIC's cost is R&D, so making 5k or 10k chips does not increase the cost by much. So "expensive" is not applicable to each individual chip, but rather to the whole effort to create and manufacture such a thing.

The $1172 1.6 GHz, 3.0 MB Madison 9M with 533 GHz FSB
gets 2692 SPECfp_base2k. That beats the top of the line
1.9 GHz IBM POWER5 with 36 MB of external custom cache.
It completely annihilates the $851 top of the line DP Opteron
(model 250) by about 1100 SPECfp_base2k. IMO clearly it
was Cray that bet on the wrong horse for HPC.

Yeah, yeah, yeah ... The trick is of course that it is way easier to build large scalable multi-processor systems with Opterons via its nice Hypertransport links.

SGI uses that proprietary thinngy called "CrayLink" to tie all the Itanium chips together. Without something complex and mature like this CrayLink, one is dead in the water when trying to build anything reasonably large with Itaniums.

Single cpu SPEC is a good bragging point, by looking beyond that is what is important here. Somehow HP chose to cancel Itanium workstations meant specifically for those looking for that high single cpu performance ...

it is demand for fullfeatured PCs performing like a desktop in a notebook-form-factor has created the segment.

Indeed, not everything can be packed in a small notebook, and not everyone needs great mobility for lotsa $$$. How they intend to kill DTR is beyond me ...

Barrett just settled the issue of whether or not they really could have produced a 4ghz chip as the PR stated.

It seems like it is not the frequency that killed them, it was the power requirements instead. They cannot produce a chip that would readily fit into the specified boundaries, so they had to terminate it.

SocketA is more than adequate for the business desktop market for a while. nVidia has a good 6-12 months before they need to seriously evaluate options.

I am not so sure that SocketA is still adequate since it is being phased out.

j3pflynn on Nvidia & IGP: but I suspect it more likely had something to do with the different interface to shared memory. The IGP chipset was very successful, and they're still being sold.

This is an interesting guess! Indeed, where will this integrated core get the RAM? Adding an extra memory module on the motherboard just for the IGP would cost extra $. Rerouting memory via A64 requires some involved engineering.

Nvidia is probably working on IGP for nForce3/4, but when is this gonna show up - anybody's guess ...

nVidia already had the name for performance with K7 chipsets and IGP.

As an anecdote, I spent many hours with one nForce2 board trying to figure out what was not working - it turned out the IGP was flaky.

If they want to sell lots for lots of money it seems very odd for them to drop IGP, and therefore, the business sector. Unless they've decided to pass on the business desktop in favor of workstations.

If not for technical reasons, they could have dropped IGP for poor profit/effort ratio. nVidia likes good profit margins, and business sector wants the cheapest of the cheapest stuff. Selling lots for lots of money and making a small loss on each sale is definitely not fun!

For whatever reason, nVidia seems to be focussing on the performance market.

They can build a strong brand name on performance chipsets. Without a name, getting into business desktops is tough.

There were no technical or thermal limitations that prevented Intel from releasing a 4-GHz product, Kirby says. But there were practical limitations, so that to release such a product Intel would have to devote time and energy to tweaking circuit designs and testing those chips, he says. That always takes place when a chip maker validates a higher speed grade, but at a certain point it's no longer worth the effort, he says.

These seem to sound an awful lot like "technical" limitations to me!

bigger chip has less heat density. So I think the speed grade will not be lost because of heat. I think this new chip will give one full speed grade.

This is bizzare. Whatever energy is converted by the chip into the heat must leave the chip via the heatsink. Thus all that matters is the total power dissipation. The heat density does not even come into the picture here.

this will be a much better core for 2P Xeons. Intel may want to attack Opteron with 2 Mb chips and economy of scale.

It's not clear how few hunderds of expensive 2Mb Prescotts made and sold might improve the economy of scale for more numerous Xeons.

Bigger cache can reduce the bus load as cache misses are less frequent. I do beleive Intel will be ok with handling 2Mb cached chips. Some added power, yes, but reasonable.

Going from 1Mb to 2Mb is smaller % performance increase than for 512Kb to 1Mb, I would say ~5% on average at most for a 2Mb Prescott vs. 1Mb. So losing 1 speed grade due to power increases performance by 1 speed grade, or, in other words - zero sum game.

The faster 1066 Mhz bus could probably buy 3-5%, but 2Mb Prescotts with 1066 Mhz bus are not in the plans. So then 4Ghz/1066 chip would be close to 4.2Ghz/800, or, in other words - a minor overall gain.

At 2.6Ghz for A64 an extra speed grade of 0.2Ghz adds 7.6% in total clock speed, perhaps 6% in performance.

Now, who was that person scaring everybody how Prescott with 2Mb was gonna be a tiger? What that properly qualified as a "paper" tiger? I can't seem to recall ...

3.2GHz/512k+2M/800 - 92.1W

From this, it looks like FSB speeds offer little to nothing in the way of added power dissipation, while cache size seems to add 5W for every megabyte.

Therefore, I would guess that all the new chips will be 115W, just like the current chips, and it cost Intel one speed grade in the 2M chips to make it this way.


Well, while the bus speeds do indeed have marginal effect on the power, the extra Mb of cache might consume closer to 10W than 5 since the dissipated power scales non-linearly with frequency. At any rate, that's just a loss of a speed grade or two.

Do those 2Mb of cache on the 3.2Ghz chip run at full speed?

Take the most idiotic conspiracy theories the 'Droids have ever come up with and roll them into one letter, and that's close to where this one ranks. He obviously has no clue what he's even talking about.

Well, the letter's language is not very clear. However, I do not see any factual contradictions.

$18 mil to IBM could have been sufficient to slow down the development of a niche product - Opteron servers.

No good benchmarks exist of EMT64, i.e. those with clear comparisons of 32 bit vs. 64 bit mode.

Evolving Prescott revisions with added features confirm that the core is still being work on heavily.

Thus I would not be so dismissive of the letter until the facts are known.

Xeon MP with 64 bits

Did anyone catch this:
http://www.theinquirer.net/?article=18504
(the last letter in the bunch)

The 2MB L2 cache chip is carrying the family code and stepping ID of the Xeon MP chip (which is also the Extreme Edition chip). This would imply that some insane person has taken all of the EMT64 stuff and re-integrated it back into the 130 nm chip, doubled the L2 cache and then shrunk that (as opposed to doing the sane thing and moving the cache coherency logic to a fresh copy of the E0 code base). This cost a fortune and it is no wonder they are a year behind in releasing the chip.

Is this person talking about current Xeon MPs, or future ones? I thought that Xeon MPs will be using the Prescott core when it moves to 0.09u. For now, however, it uses .13u process, and the Northwood core.

On the other hand, adding EMT64 to Northwood and shrinking that is not such a bad idea. That would be a much better core than Prescott.

idf has always tended to show something conceptual (and to be worked by yet another working group with a spec to be produced in a year or so...) or about to be introduced in two to three months. the year or so out product stuff was seldom shown and was available only under nda.

Exactly my point! Where was the conceptual dual core shown? What architecture would it be based on? These conceptual questions were not answered ...

your conspiracy theory is just that. ndas are used selectively by both amd and intel.

Perhaps, you simply missed the point of my post?

Intel's capitalization has a large premium build in based on the assumption that they will indefinitely be the market leader. They simply must maintain such an illusion at all costs, and showing off new technology at IDFs is what they always did. I am not sure how NDAs are relevant here ...

True, but don't you think that Intel gives their customers more information under NDA than is announced at IDF?

My conspiracy theory tells me that IDF is really the place for Intel to show the best they've got. This is how they always acted before - a historical trend that can be easily verified. Intel is a public company with huge capitalization, and informing investors of their clear future plans is the best policy. NDAs for selected vendors simply won't cut it ...

wbmw - dual cores In other words, you think that because Intel hasn't outlined specific processor roadmaps at IDF, that they have no plan for the future. What were you expecting? A more detailed demonstration of a dual core design would have been more convincing, but just because it didn't show at IDF, it doesn't mean that it is >18 months behind AMD, as your post seems to suggest.

Well, things take time to design properly. That just seems to be how the world works in general. IDF is a really important show for Intel, so the fact that they had nothing indicates that they are behind, by how far - it's anybody's guess. P4 core sucks for dual core chip purposes, P-M lacks many features. So factor that in.

Now consider what would you do if you were a server vendor. Hearing "trust us" from Intel is not going to alleviate your concerns. You'd most likely start designing Opteron systems, and at the first sign of Intel's lateness with dual cores you'd be selling those. Since you'll have to sell them with dual core Opterons anyway, might as well start as soon as possible.

Some guys already trusted Intel with Itanium. SGI almost went under because of that. HP still cannot decide which way it wants to go. Anybody with half the brain would start hedging the bets after this IDF.

Dell's decisions will probably tell us how substantial AMD's lead with dual core is, it'll have to be pretty hefty for them to opt in.

Of course, this would only happen when the dual cores show up. Until that time Dell can happily sell Noconas and receive $$$ for Intel. And by the time we know about Dell there should be plenty of other information around about AMD's lead in dual cores.

I actually think that Sun is the key to the server market. Lots of people have fond memories about Sun's enterprise support, and will stick to Sun if given an opportunity.

Horus chip: Like I mentioned before, it looks like this 8-way system could be Horus-enabled for not much more than the cost of the Horus chip itself, as the processors modules are connected through slots to what looks like a nearly passive HTT interconnect backplane.

That would be a very sweet system if the guys can deliver! It would also kill all the RISC vendors around that sell large systems. AMD could be a monopoly in this market

mas >16 way systems

My first impression when seeing this config is that AMD is about to commoditize the > 2-way server space bigtime with this particular config a possible 16-way with dual-cores. Only really big IT sites need > 16-way for any one server application. Sun says they have interesting designs too coming up.

There is a nice market for > 16 way systems in scientific computing. Now people buy faster interconnects that raises the price per cpu by at least a factor of 2. Obviously, this money could go toward other components of the system. And if one could buy a 16-64 way system for the price of the 16-64 dual nodes with regular 1Gbit, the demand would be very substantial.

wbmw: The timing of the dual core launch may have some PR value for whomever is first, but to make an actual difference in the market, AMD would have to be >1 quarter ahead of Intel. OEMs aren't going to be abandoning their Intel designs if Intel's dual core chips come out 2 weeks later than AMD, or even 4 or 6 weeks.

Well, it looks like after this IDF OEMs MUST already BE seriously reconsidering their Intel designs. Intel's message with "we will do this, we will do that" with no clear info on what their dual core is going to be like did not sound very convincing.

For a server maker, it is a no brainer to go with Opteron at this point and be reasonably confident that the products 12-18 months down the line will still be competitive.

In my opinion, Intel's present loss of clarity is what is going to hurt them most. Before, whenever AMD got ahead, they always had something decent in the pipeline so OEMs could hold out. Now, however, Intel is behind, and what is much worse, there is no hope in sight!!!

It is going to be quite fascinating to see how Dell handles this. They are stuck between Little Rock and the hard place

People suspect that the new 90 nm Hammer core is optimized by yields rather than binsplits. Proof: they already ship 90 desktop & notebook chips, but the upcoming FX-55 and A64-4000 are both 130 nm. AMD is trying to increase the output, confirming our information that A64 is production-bound at present

There is lots of money to be made in ~$200+ consumer cpus and even pricier Opterons running at "only" 2.0-2.2 Ghz using 90 nm. With no faster chips from Intel, AMD will surely maximize the overall revenues.

Dan3: A $20K Opteron box ($10K if it's a lowballed Tyan based box) has 34GB/sec of aggregate bandwidth. It can easily and concurrently handle an assortment of dual port 4GB/sec (duplexed) fiber channel cards and a couple of 10Gbit/sec NICs while barely touching the memory bandwidth.

Compare that to a Xeon MP box with it's aggregate 3.2GB/sec of bandwidth or an Itanium box with 6.4GB/sec of aggregate bandwidth.

And it is not just the theoretical bandwidth that matters, the actual performance is far more important. Quite a few people here have recently built clusters with 2 single P4 motherboards per 1U box and 800 Mhz FSB in order to "manually" resolve the bandwidth issues in dual Xeon boxes, where up until very recently FSB ran at 533 Mhz.

Opteron demand is strong - a datapoint

I had a chat with a sysadmin at a very well known smallish private university. It appears that everybody and their brother are getting Opteron clusters in the range of 32-200 cpus. Some guys are also considering Apple's clusters based on the strength of IBM's compiler for Power chips.

The funny part is that nobody is interested in current Xeons (64 bits or not), and no Itaniums2 are in sight. The latter are not cost efficient, while Xeons are nowhere in sight to be tested.

Me thinks that just cluster guys buying Opterons in such numbers can generate good volumes.

Now, remember that these are not your average server buyers. These people test a lot before they buy, do not have to follow any corporate BS policy such as "Intel only", and could care less about "nobody got fired for buying Intel".

90 vs 130 nm - why hurry?

"The biggest benefit of 90nm for AMD is the potential for increased capacity. Any thermal, power or scale benefits are just gravy."

Actually, while 90 nm process is being perfected to produce at least as many good chips per waver as from the 130 nm process it makes sense to keep making 130 nm chips and switch fully only when things are really smooth with 90 nm. There is no need for IBM style supply problems here.

Also, 130 nm and 90 nm chip revisions are made to be almost identical in order to ship them interchangeably.

Re: InfoWorld review -- One of the reviewers was clearly biased by financial conflict. This was not a workstation test. This was a HyperThreading PC test (and hatchet job). Perhaps then the reviewer would have been sent an Opteron 2P server e325 optimized for that work.

Well, there is a thing out there they call "peer review". This article would never pass any. No numbers, no reproducible testing techniques. Just a bunch of random sensationalism thrown together. Somehow when reading the article my BS detector goes way off the scale.

Any financial conflict or not - the authors are clowns who cannot put together a decent piece of FUD that would at least appear plausible to a person with traces of common sense.

Anybody knowledgible getting a Prescott now?

Looking at the Intel's roadmap
( http://www.theinquirer.net/?article=17797 )
it appears that it is very tough to be a knowledgible buyer
and go for a Prescott chip now. Even if the "no execute" thing does not protect much, I'd still rather have it. Another point is the x86-64 support, before I spent money on something, I'd very much like to know how it actually works in 64 bits. Last, the power consumption. I've been few times in offices which were somewhat undercooled, and being slowly melted due to the workstation heat is a feeling familiar to me. So I would prefer to avoid that as much as possible. Also, cluster users tend to pack more boxes in a room than the A/C can handle. I know of a cluster where only half of the boxes were running to keep the heat at reasonable levels, because the A/C could not be upgraded for some time.

So, overall, getting an Athlon64 or Opteron is a no brainer.
One might reevaluate the situation around mid-January, when things settle down a bit for Intel, but for now - there is no consideration. Why get a half-baked product?

What do you guys think?

Re: dual core plans

http://www.xbitlabs.com/news/cpu/display/20040805000817.html


Well, but how realistic can this thing be? It appears that the announcement could have been designed to keep PC makers from jumping the ship rather than anything actually real. It appears as if they were gonna sell such systems in mid-2005, they should already have some prototypes by now, and know for sure what the core would be.

And if they have dual core Prescott ready to go, would you guess what the power budget of such a beast would be?

wbmw - You can't claim that a 2.6/2.8GHz Athlon 64 mid-way through next year will be that much farther ahead of a 4.0/4.2GHz Pentium 4/2M/1066MT/s processor than they are today. Therefore, you can't say that Intel has no response for the foreseeable future.

Intel's response is easy: continue to ramp Prescott and derivatives until they can ramp 65nm by the end of 2005, or by Q1 2006 at the latest. They should have enough speed revs and cache sizes left before they get left hopelessly behind in performance.

Well, the game can change substantially with dual core chips, if AMD manages to deliver these ASAP. Prescott is unlikely to be packaged like that since it generates too much heat already in the 1 cpu form. So it might be that Intel CAN be left hopelessly behind in performance, if only for several months. But this is all speculation at this point

wbmw - That's why I don't underestimate Intel's ability to make underwhelming processors a success, especially when the AMD choir starts recommencing their hymns about "dud" processors.

OK. I see your point related to the semantics of the word "dud". Nonetheless, in order to make the underwhelming Prescott a success, something has to happen that would improve things relative to the AMD offerings. They either have to increase performance substantially, or scale it to much higher frequencies. None of these things appear to be realistic at the moment.

Sure, Intel has lots of inertia with the PC makers, but it won't last forever if they keep offering underwhelming cpus ...

The problem with Prescott appears to be not only that it is an underwhelming cpu right now, but also that it is very likely to stay such in the foreseeable future. If you disagree with this statement, please, explain how it could be made an "overwhelming" cpu.

I looked, but a lot of those comments actually miss the point. While there is a problem with choosing the 3500+ instead of the Opteron 150, the *real* problems are that the results are completely bogus!

Yeah, choosing different classes of cpus was apparently a very useful diversion - lots of people jumped on this mostly irrelevant issue, and missed the bigger issue of the bogus numbers

Anand got lots of damage control to do once he is back!

A straight shrink to 65nm will probably yield no more than 4.266 Ghz or 4.4 Ghz at a stretch.

Well, what good is frequency headroom if the heat makes those frequencies impractical in the first place?

wbmw - Ooouu, the famous "dud" word. It's like deja vu, all over again.

Anytime

But can you actually substantiate why it is not a dud? What things other than divine intervention can make this brick fly?

wbmw - No, Prescott's a brand new, aggressive design that is as unfit for 90nm as Willamette was for 180nm. You might find that a 65nm shrink will do wonders for the design.

That sounds more like wishful thinking rather than reality ...
Indeed, Willamette was too large for 180 nm, and had only 256Kb of cache.
130 nm shrink gave it a lot of frequency headroom, and 512Kb cache. AMD could
not keep up, and faced the consequences.

Prescott, on the other hand, is dud for life. As is it's too hot for frequency
scaling even to 4Ghz. It needs lower voltage to get there, and it is not
easy to stabilize it at such low voltages so that the power consumption is under
control. It also does not need more cache, since 1Mb is already a lot. Another
1Mb will give insignificant returns. The 2Mb Extreme Edition P4 is pretty much
a joke, it is hard to imagine a more brain dead "performance" solution that this
one. Prescott's die is not that large either, so what good would 65 nm do?

Intel is in a double bind here. Cool Northwood can't be taken to 90nm because it
does not have x86-64 - at this stage a very needed feature. Dothan is too feature
poor to become a full blown competitor
to K8 in a short period of time. That leaves Prescott to hold the lines regardless
of how much it sucks. If Intel thought that another shrink would save the day,
Tejas would not be cancelled, since Prescott and Tejas are similar breed. Stellar
performance of Prescott at 65nm would imply similar things for Tejas, and we know
that this poor thing was put to eternal sleep.

Realistically, the only viable competitive solution from Intel for 65nm is the
Dothan core with bunch of added features and x86-64, perhaps with on-die controller
and dual cores. Quite a bit of engineering! Such a Dothan on steroids is unlikely
to show up for 90nm, it is kind of late for that if it has not even
taped out, and that baby will need lots of debugging since it's a brand new design.
AMD would have to have a Prescott-style fiasco with K9 to lose the 65nm
game. Sure, they can be late with the 65nm, and that might hurt them. I would
say, however, that AMD's core advantage at this stage more than compensates
for the process disadvantage that they have.