Looking at Intel's Prescott die.


http://www.chip-architect.com/

JoeP

I thought the plan was to breakeven for the end of Q2. Isn't this still true?

You believed that?

Don't forget, it was also the plan to announce Hammer in 2001...


EP

Spokeshave -

As SOI was AMD's "hail mary", so will strained silicon be Intel's "hail mary".

Hardly. Intel is not going broke. Intel had an SOI process 3 or 4 years ago that I was aware of and Intel chose to go another route. Intel develops their own process technology and I expect that they have made the right decision for 90nm. People claimed that Intel was having problems with .13u but never provided any evidence to support that. We'll probably see the same round of claims again and you're just getting a head start. I already turned out to be right, as I always do, but you have to wait a long time to see how you fair.

I will make a comment but I am not directly an expert in fab processes.

When AMD announced they were going to use SOI for Hammer the industry was a bit shocked because SOI was known to be expensive, problematic and the yield was questionable, as were the benefits. Why do it? The concensus was that AMD could not be competitive on bulk silicon and they were doing a "Hail Mary" all or nothing play. It was an extreme risk but the alternative was to get out of the CPU business, so there seemed to be nothing to lose. All was lost anyway otherwise. At the same time Intel said SOI was not in their plans because of the cost, difficulty and little benefit it offered. We had many discussions on the old SI board, including experts in the process field. We all predicted long delays, poor yield and extra expense leading to heavy losses. We did not accurately forecast the performance problems that appear to affecting ClawHammer but I guess that should have been obvious looking back. I was just about the lone voice predicting Hammer's performance wouldn't live up to the hype and I still stand by that position. I think we did a pretty good job of predicting how this would play out but the details remain to be seen.

EP

wbmw -

The article CJ pointed to was using 2.2GHz Prestonia Xeons with 512K L2 and both with and without iHT enabled. There were also older Foster Xeons.

Gollem -

todays Xeons are much better? What exactly is the difference between the old and new?

Mainly frequency but perhaps the newer SQL was more optimized for iHT? Just a guess though.

EP

KD -

You must admit that it must have looked pretty strange to me, especially because I made quite an effort to get my board known (Amdboard, Aceshardware, SI, etc.) As my board now has permanent links and even a newspost at AMDBOARD.COM, I suggest we use my board and moderate the one board together. Should be the best thing, imho! What do you think? It will be hard enough to get activity to one board, let me assure you that

Keith, this board existed long before your board did. Why did you start a new one anyway instead of just pointing people to the existing one here like Spokeshave and I did? I didn't start my own board. I prefer to think that the board doesn't belong to anyone and I see much too much emphasis on you owning your board.

EP

Spokeshave -

Comb_Jelly posted the first benchmark and asked for SQL tests. Here's what wbmw was responding to:

There aren't many sites that have benchmarked using SQL Server. If you can dig up some proof that Xeons can outperform Athlons on this benchmark today, point 'em out. Inquiring minds want to know...

Spokeshave -

There were 5 tests, not one. CJ asked for a SQL test and he got 5 and in all 5 the Xeon blew away the Athlon. If you have some more recent tests then you are welcome to present them.

EP

CJ

I assume by now you've seen the more recent benchmarks. I think they speak for themselves.

wbmw -

The Athlon really sucks wind. It's blown away across the board! Shows you what an updated article can reveal.

Paul -

I suspect... I'm confident... if... when...

Things never seem to change...

CJ -

According to Anadtech, Athlons outperform the Xeon processors with 512k cache, even when HT is enabled.

That article is almost a year old. Today's Xeons are much faster and perform much better compared to the Athlons.

EP

wbmw -

AMD has only $1 billion in cash and equivalents, and $1.8 billion in long-term debt. Geraghty estimates that if it keeps to its current capital-spending plan, AMD will use up $800 million of that reserve in 2003 -- with no plans to turn cash-flow-positive until mid-2004.

As they say, do the math...

Spokeshave -

it looks like AMD paid IBM $46MM to fix SOI...

That must be why they pushed Athlon64 out to Sept...

facsnotfiction -

If you are who I think you are you will find that your style will not go over well here. You will get the boot much faster than you did before.

This is your chance to start over. I will even leave you off ignore if you behave yourself. Here's an opportunity to actually communicate and get your points across. I suggest you respect it.

EP

Spokeshave -

the most interesting thing is the big L3 cache bus. I wonder where that might be leading.

It's no secret that Intel uses the same base die for their Xeon products. With the L3 interface they are positioned to add cache cells for the large cache MP Xeons. With a tiny die size of 87mm (according to the article) they could easily add L3 to their desktop version should AMD actually be able to produce a competitive Hammer. Hypothetically speaking of course. This is just an extension of the NorthWood which I believe does the same.

EP

Spokeshave -

I post on other boards here, and the degree of censorship seems to depend largely on the discretion of the board "moderators".

That's my impression too. I've become more comfortable with the way this forum is managed. We had a few problems at first but it seems to be pretty reasonable now. Only the abusive and unreasonable posters will suffer here, was it should be. The real difference is that we won't have to ask for posts to be deleted and abusive people will be shutdown quickly but we'll have plenty of opportunities to debate amongst ourselves.

EP

Good luck.

I hope you guys find a more suitable home here. Be aware that this board uses censorship to an extent not seen elsewhere. Courtious, on topic posters will have no trouble here. Others won't like it.

burn2learn -

Sorry but I don't quite understand what your question is.

Are you saying that 300mm isn't suited for a .13u process? I'm sure you can understand that I can't comment on Intel's yields or defect density here.

EP

Alan -

I also find this a bit baffling. The only thought I had was that the 875 is on a more advanced litho than the 865. I would assume 865 is on 0.18u and the 875 on 0.13u. This would result in a premium due to the limited 0.13u capacity.
Does this seem reasonable?

Reasonable to you and me maybe but reasonable to Intel? My guess is that they prefer to not do 2 designs. As for limited .13u capacity, it's hard for me to look at 5 monster fabs, 2 of them 300mm and think of capacity problems<G>. Also with the Willamette die winding down more .18u capacity is freeing up. That's what the chipsets do best, use freed up capacity.

Check out the new AMD board.

Where?

wbmw -

RackSaver, AMD heat up the server wars

Let the games begin.

Whatever Happened to Transmeta?


http://story.news.yahoo.com/news?tmpl=story2&ncid=1211&e=1&u=/nf/20030305/tc_nf/20911&am...

Spokeshave -

I'm confused. Why would chipsets be speedbinned at all?

My post was speculative in nature and I don't have an exact answer. I don't know enough about the designs to be specific however there are instances where higher performance was possible but impractical. The 400BX chipset had a governer in to to throttle performance under some situations. Unrestricted, it could have melted under a unique set of conditions.

Take my post as the speculation it was.

EP

wbmw -

Essentially, they are able to skip a number of stages in the memory controller using new design optimizations. It cuts down on latency, which improves performance. The reason why this was not built into the i865 chipset could be several reasons. 1) It's a new technology and Intel did not want to risk it on a high volume chipset. 2) Intel wants to charge a premium for the technology, so they want some differentiation against the i865 besides the ECC support in memory.

I can speak freely on this one because I really don't know for sure how they're doing it but what you describe can easily be done in a single device with fuse options. It would also save the trouble of designing 2 different devices plus there's the lingering question of why not speed bin chipsets if a percentage of the functional units might perform at a higher level? Either way, you could be right in this case but the bigger question remains a good one.

EP

Dew -

Why hasn’t speedbinning previously been done for chipsets?

Traditionally, chipsets have been manufactured at Intel on second generation process technology, with second generation manufacturing all the way thru the system. That doesn't mean second rate quality. This was the way that Intel made use of technology that was no longer cutting edge but already depreciated while still being usefull for non speed critical application. Designs were always targeted to yield 100% to the target speed, but I've always wondered why this restriction needs to be enforced. Speed binning isn't that big a deal. The actual speed determination is a relatively small part of the total test. If it doesn't pass the speed test at high speed then slow it down and try it again, then bin it out accordingly. Some other controls need to be in place but with Intel's volumes of 100s of Millions of chipset devices it can be put in place. Pretty elementry. I think it is long overdue. When you think about it, why restrict yourself to requiring that 100% of the functional units all meet the same speed when you can raise your target and get some binsplit to the higher performing part? If it makes sense for Processors then why not for Chipsets? You've lost nothing whatsoever because you only need to require that 100% of the units meet the lower speed. The higher speed part is pure gravy. If a higher speed Processor demands a premium then the chipset should too, espically if it provides the same over all performance improvement as a speed notch at the Processor level. The 875 seems to do this.

EP

Intel Speedbinning chipsets now?

http://www.xbitlabs.com/news/story.html?id=1046783261

All the performance enhancements are achieve internal to the Intel 875P chipset.

For what seems like forever manufacturers have speedbinned processors, but not chipsets. Why? It looks to me as though Intel now sees that some of their chipsets can rise to the next level of performance though not 100%. While Intel is not specific about the exact nature of the "internal enhancements" I have long expected to see speed binning brought to the chipset world. This may be the first example. If I am correct, this is perfectly valid and long overdue. Whatever it is, it looks like the new chipsets bring new levels of performance equal to a processor speed bin.

EP

http://www.crn.com/sections/BreakingNews/dailyarchives.asp?ArticleID=40286

Intel Exec: Xeon Channel Sales On Pace To Double

By Edward F. Moltzen, CRN
San Diego
9:49 AM EST Mon., Mar. 03, 2003

Shipments of Intel Xeon processors in the channel are on track to double this year as Microsoft readies its Windows Server 2003, according to one of Intel's top channel executives.

Steve Dallman, director of Intel channel sales and marketing, also said the chip giant is getting closer to shipping Pentium 4 processors at 4GHz. Dallman addressed a gathering of Intel solution providers and systems builders at the company's annual Intel Solutions Summit here. "There is nothing between us and 4GHz but months," Dallman said.

Dallman addressed a gathering of Intel solution providers and systems builders at the company's annual Intel Solutions Summit. Noting the difficult economic environment the industry has seen over the past two years, Dallman provided an upbeat assessment of Intel's channel's health and opportunities. During the conference, he and other executives plan to roll out the company's channel and technology road map for the coming year.

Key to those opportunities could be Xeon, Intel's 32-bit processor for servers and workstations. Dallman noted that Intel is readying two, new Xeon processors at 3GHz or greater, and said sales to date show strong growth. Intel's channel grew from the sale of 33,400 Xeon processors in 2001 to 340,000 last year, he said.

"We think we can do [two times] that in '03," Dallman said. The current run rate of Xeons in North America channels is 760,000 units for the year, he said."It's a huge opportunity, and we can make a lot of money at this," he said.

In addition, Dallman noted the continuing pressure on business IT departments to upgrade desktops. "There's a huge PC opportunity that's beginning to build," he said. If last year's flat-line sales numbers in the desktop space continue in 2003, Dallman said, 50 percent of all desktops in 2004 will be more than three years old. If a significant upgrade cycle doesn't begin this year, he said, "there's not enough capacity in the world to take care of all the demand in 2004."

wbmw -

should I assume that "sequentially" means the fourth quarter, relative to the third quarter?

I hope so.

This article says Intel is now running 50nm channel lengths.



http://www.e-insite.net/semiconductor/index.asp?layout=article&articleid=CA279104&pubdate=3%...

HP Holds No. 1 Worldwide Position for UNIX, Windows and Linux Server Revenues

Leads in Worldwide Standard Intel Architecture Servers, Blade and Itanium Revenue -- Ties in UNIX Revenue

http://www.hp.com/hpinfo/newsroom/press/2003/030228a.html


HP's Itanium 2 system shipments increased sequentially 364 percent, demonstrating increasing acceptance of both technical and commercial customers;

Spokeshave -

You be sure and let us know about all those companies that do guarantee sucess.

You'll be the very first to know...

Dew -

the TC1000, despite the supposed marketing drawback of having a Crusoe rather than a Pentium inside, holds the leading market share among tablet PC’s by a wide margin.

Slow indeed and very perilous. Being an misunderstood underdog losing money with a good new product coming out "soon" is no guarantee of success. Good luck.

EP

DD

the TC1000, despite the supposed marketing drawback of having a Crusoe rather than a Pentium inside, holds the leading market share among tablet PC’s by a wide margin.

So why can't they make any money?

Subzero -

You remind me of someone... Just can't put my finger on it...<G>

Windsock

This leaves us scratching our head over the entire product naming scheme.

As has been said before, when a company has lost market share, sold off nearly every asset available including their headquarters building, posted by far the greatest loss in their history, delayed their new product line 4 or 5 times and is on the brink of bankruptcy, there is little to be lost by misrepresenting their aging products.

EP

I have been around. I think wbmw is a bit busy right now...

Ahhh the Paul we all know and love.

Spokeshave, it would help if you provided a link.

I realize you misread the date, but this stepping release is normal. For your information, Intel has a number of steppings in the works as we type. I know of 4 in production right now and as many in varying stages of qualification. All address different issues but improved binsplit is usually common to all of them. Some are simply a metal routing change to improve speed. Those don't require notification to customers because there's no logic or specification change. Others may be to accomodate a different package. Some are a full mask layer change to take advantage of process improvements and some may be only to improve ESD protection. Some may fix errata. Still others may be for reasons that might be discussed at a later date.

EP