Intel Corp (INTC)

[Elmer Phud]

wbmw -

Essentially, they are able to skip a number of stages in the memory controller using new design optimizations. It cuts down on latency, which improves performance. The reason why this was not built into the i865 chipset could be several reasons. 1) It's a new technology and Intel did not want to risk it on a high volume chipset. 2) Intel wants to charge a premium for the technology, so they want some differentiation against the i865 besides the ECC support in memory.

I can speak freely on this one because I really don't know for sure how they're doing it but what you describe can easily be done in a single device with fuse options. It would also save the trouble of designing 2 different devices plus there's the lingering question of why not speed bin chipsets if a percentage of the functional units might perform at a higher level? Either way, you could be right in this case but the bigger question remains a good one.

EP