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kpf - dont think it is an anticipation but a strategy to outproduce competition using its capital and expected 300mm cost advantages. Not sure how exactly they intend to do that. Doubling cache sizes every year is not sufficient to explain the capacities they are building up.
Let's look at that capacity: The most common estimate I see for Prescott is a little over 100mm2. If Intel has very good yields (that's if) then they would get around 475 good Prescott die from each 300mm wafer. If a large fab has a capacity of 6000 WSPW then they could produce nearly 40 million per quarter from each 300mm Fab! I count the following 300mm fabs that will be operational by end of next year when Prescott is fully ramped: F11X, F12, D1C(with a new name), Ireland (with a new name). So if one 300mm Fab could theoretically supply most of the uP requirements, what are the other 3 Mega Fabs for? And this doesn't even include the other large 200mm fabs, F11, F17, F18, F20, F22, IFO etc, not to mention the Flash Fabs and old legacy Fab(s).
What are they thinking? I'd love to be a fly on the wall at one of Intel's long term forecasting meetings!
Larry - Reading Bob Brinker's Letter of 4/5/03: (1)Clearly shows he recommends buying MSFT at 23 as of 3/11/03
Are you violating Bob's Copyright by posting that here?
Sgolds -
This is all from memory so I may have mispoke. IBM may have a perpetual x86 license but they don't have the design. They could design and produce their own but it won't be Intel's design database like in the 286, 386 & 486 days.
Back in the days of the K6, AMD directly licensed Intel technology, sharing the same sockets and motherboards. My impression is that the 20% licensing limitation may be something from back then, before AMD really independently developed processors. Now the percentage may be larger, or perhaps jettisoned totally in more recent agreements.
IIRC this issue was discussed when Jerry announced the UMC deal and he indicated there was some restriction in place but he wouldn't elaborate.
Sgolds - While there may be a clause in AMD contracts with Intel to produce x86 technology, my general impression is that IBM has all the same rights to the technology as AMD. Recall that IBM used to produce Intel processors as a second source, and I remember them updating their license long after they stopped producing them. Thus I doubt if this is a blocking issue for (the speculated) concept of IBM buying out AMD.
I'm going by memory but I believe IBM let their license lapse when they thought PPC was going to take over the world. Previously they had been licensing each x86 generation one at a time. Now, their process is very different from Intel's and it would be very difficult if not impossible to do a conversion. As for AMD outsourcing to IBM, IIRC there is a limit to the % of their processors AMD can outsource.
However, IBM does not want to see Intel have a full monopoly in x86, nor see Intel in the position of dictating that the market move to Itanium, so it is in IBM's best self interest to cooperate with an independent AMD as a counter to the Intel-only alternative. Of course, AMD has to do their part with a valid design (K8 and K9), IBM certainly doesn't want another Cyrix fiasco. Thus technology exchange on 90nm and joint development of 65nm (with potential for joint manufacturing later) makes sense to me as the goal of their cooperation.
I agree but as I said above, x86 licensing agreements with Intel may restrict the volume IBM can contribute.
Sgolds - Perhaps they expected (and still expect) Itanium to take off?
Does this mean that AMD doesn't build because they don't expect Opteron to take off? Just joking... AMD doesn't build because they don't have the money. Pretty simple.
IMHO, Intel has been planning their 300mm 90nm with the expectation that Itanium would be a growing presence on the desktop by now, and they really haven't brought their factory build plans in line with realistic expectations.
I assume you realize that Itanium isn't on 90nm but imply that Intel expected Itanium to use up much more 130nm capacity, requiring added Fab space for 90nm? I don't think this is the case because the cost advantages of 12" are so compelling that it's unavoidable if you can afford to build it. I also don't believe Intel expected Itanium volume to have a major impact on capacity at the time the 90nm/12" commitments were made. Intel is expecting something else and you may believe their expectations are unrealistic but only time will determine who is right.
If my suspicion is correct then Intel will not open all their new conversions on the expected timetable. They will not man overcapacity to the point where they can not cover the costs of production, and I just don't see what they are going to produce with all that capacity.
May we live in interesting times...
CJ - Nor have you [RGood] made any case for 300mm. Sure, it helps cut costs, but it is of no use to AMD if a) SOI wafers aren't readily available in 300mm and b) they aren't running at capacity in their fabs. To do it just "because Intel is doing it" isn't really sufficient. Now at some point they'll have to use 300mm because the equipment they need won'y be designed for 200mm, but that time isn't now. Which is why they are researching it.
You don't wait until you need something to build it, not when it takes ~2 years. Why did AMD think they needed it enough to do a joint venture with UMC but then change their mind and decide they didn't need it? Intel is still adding capacity at a fast pace. A huge 12" just came on line (F11X) plus another ready and waiting to turn on the tap at 90nm (D1C) and 3 more in construction/conversion, (D1D, F12 & Ireland). What is Intel thinking? What do they anticipate that AMD doesn't?
BTW: I think the term "Jihad Jerry" is appropriate here because it captures the essence of AMD's business plan over the last 20 years. Anyone who denies that hasn't been paying attention.
UnD - So, if the compilers do not produce much better SPEC scores, we may see little movement in the stock price
Do you really think the stock market values AMD based on SPEC scores?
Rgoog - which failed once before with TSMC)
I think it was actually UMC.
Petz: chipguy made it sound like the EDAC and redundancy features on the L3 were so robust that the whole L3 always worked.
Maybe it does?
Joe - If your prediction is that the outcome will be less than what AMD investors predict, that has the probability of this prediction being correct that is about equal to the probability that the sun will rise tomorrow.
I'm sorry you didn't get any more out of it than that. My conjecture is that AMD's ability to manufacture Opteron/A64 is less than it would be for a non-SOI equivalent without the frequency pressure the current Opteron is under. Two major factors affecting output. SOI and frequency. Either one alone would negatively impact yields.
As is the probability that the first yields on new generation of process having lower yields than a yield on a mature previous generation process. Or yields likely being lower with higher number of metal layers as it would have been with lower number of metal layers.
Great! It's obvious to you now looking backwards. It was obvious to me 2 years ago looking forwards.
ChipGuy - There are a lot of personalities here that have known each other for years. Many of us used to hang out on SiliconInvestor.com. For one reason or another people have moved over here. Most but not all have kept their old aliases. Many of us are well acquainted.
Petz - Does the 3M L3 version of Madison have the same layout?
Sheeze! Haven't you figured out yet that they're the same die???
Joe - Can you summarize what your opinion is? (just to see how it differs from the prediction I came up with). You can fill in your data in my table.
I don't want to predict actual numbers because the variables are too great. First off, I think Athlon yield is probably quite poor because for maximum frequency AMD has to target their transistor channels tighter than they can reasonably control. This leaves in question how much capacity is left for Opteron/A64. Concurrently I think Opteron/A64 suffer the same frequency problem and targeting fast transistors just compounds the yield problems inherent in a SOI process. Because of Intel's runaway frequency headroom (still more frequency left on .13u IMHO) and the impending introduction of Prescott on 90nm, AMD is in a very very tough position. As I've said, AMD process engineers aren't flakes. In all likelyhood AMD could produce high volumes of slower products with low defect densities, but because the market doesn't want them they have no choice but to push their process to the ragged edge and that means significant yield loss over and above the expected lower SOI yield compared to a similar bulk process. 9 Metal layers are 50% more than Intel's 6. I would think that means that any metal and via related yield loss would be at least 50% higher for AMD, maybe more (process experts feel free to jump in here).
So I don't want to try and predict volumes, just suffice to say that they will be lower than they would otherwise be if demand were not the limiter. If demand is the limiter then I don't think that is any better news.
Keith - so you basically think that the entire retail channel is just an "excess inventory dump"?
No, just PriceWatch. It's more of a flea market than anything else, IMHO.
Joe - Do you remember the predictions I made for Hammer starting a couple of years ago on SI? Did I nail it perfectly or what? We can throw up tables and projections until the cows come home. I've given my opinion and you and others have given yours. We'll just have to wait and see how this plays out.
Keith - what opinion?
This one.
and to suggest that they only dump excess inventory into the market is utter nonsense, I´m sorry to say.
Keith - Many of the vendors listed on pricewatch are official AMD channel partners, and to suggest that they only dump excess inventory into the market is utter nonsense, I´m sorry to say.
I have no doubt that AMD can produce Opteron in the 1,000s or 10,000s but that's not high volume. So you are entitled to your opinion and I'll leave it at that.
Morrowinder - SPECRATE INT:Narrow Opteron win vs. Xeon MP, Madison destroys
I think you made a mistake here. Xeon wins that one too. 26.4 vrs 24.3 in 2-way and 46.2 vrs 46.1 in 4-way.
Joe - Opterons / Athlon64 can potentiall sell chips with defects in other places outside of L2 such as dram link, aHT links, and, in case of substantial or multiple defects in L2. There will be CPUs with a single memory channel, with a single aHT channel and with 256K L2, which all can be salvaged Opterons.
Can you say A64?
Petz -Unfortunately for Intel, the "memory can handle defects" argument also applies to AMD, where a similar proportion of the die area is cache memory. So Elmer's "3.7x (IIRC) higher cost" argument still applies.
Please note that I said that applies when both products are on the same process. AMD uses a 9 metal layer(Cu) SOI process that has not demonstrated that it is suitable for high volume manufacturing. Madison is on a 6 metal layer (Cu) bulk silicon process that has already produced 100s of millions of NorthWood and Tualatin processors.It is still possible that Intel's Madison cost is very close to Opteron's cost.
Joe - Where did you get the idea of low output of Opteron? If you want an Opteron, you cen get one, or 2,000, or 10,000. If I wanted to pursue this argument, I could ask about reasons for low output of Itanium, but obviously both of us know that both Opteron and Itanium are demand constrained not supply constrained.
Just because they are available on pricewatch doesn't mean much. That's a flea market for excess inventory. With no significant design wins it's no surprise that there are plenty for sale on PW. Demand constrained, probably but it's a good think too because I don't think AMD can make them in any volume. The long delays and absence of A64 tells me AMD can't produce them but I know you guys would prefer to attribute these things to lack of boards, no Win64, Intel threatening OEMs etc.
Itanium on the other hand was never intended to be the high volume product and I'd be the first to say that Intel couldn't meet the desktop demand with a 374mm2 die.
ChipGuy - Thanks for the explanation but what I meant was the term "sub-block redundancy" as opposed to "row and column redundancy" was a new concept to me. How does it differ?
A more complex and realistic example has to include Poisson
probability of multiple defects and the ability to repair more
than one defect.
Let us also note that if we assume that defect density is particle driven with random distribution, then a wafer with X die and X/2 defects will result is over 50% logic yield because some die will capture more than one of those defects. This brings us to the question of AMD's low output of Opterons. These guys aren't flakes and we must assume they have their particulate defect density under control, so how do we explain the low output? I have my ideas but I'd like to hear your's.
ChipGuy - L3 is protected from defect failure by
sub-block redundancy, a technique superior and more robust than
the row and column redundancy techniques used in uPs (and memory chips) prior to I2.
That's a new one on me but I'll take your word for it. You would know better the I would. My observation has been that cache arrays yield better than their equivalent sized logic area would on a given process.
Petz - Thanks for some honesty. Isn't Intel making Itaniums on 12" wafers?
I can't comment on that but if they are then the cost would only be lower.
<a SOI wafer ... shows lower frequency>
Opteron SOI: 1.8 GHz as of 4/03
.....................?.? GHz as of 8/03
Itanium bulk: 1.0 GHz, no, make that 0.8 GHz as of 4/03
.....................1.5 GHz as of 7/03
Come on John, you know what I meant. Athlon runs at 2.2Ghz and Opteron with an Athlon core can't get above 1.8GHz.
wbmw - What's your speculation on this? There seems to be a lot of wiggle room in this statement.
I'm at a bit of a loss. Where can they go where they won't compete with Intel yet still have enough volume to be worth it? Do you think they might be doing something for Opteron?
wbmw - This must mean that Intel is back in the driver's seat in terms of server chipsets.
That's my take on it too. Here's another interesting quote fro that release. Broadcom must actually care about their shareholders.
ServerWorks engineers are working on plans for new server chips that won't face competition from Intel, he said.
Stock of Irvine, Calif.-Based Chip Maker Plunges 11 Percent on Intel Concerns
IRVINE, Calif., Jul 24, 2003 (The Orange County Register - Knight Ridder/Tribune Business News via COMTEX) --
Broadcom Corp. shares posted their biggest decline in over a year Wednesday after the chip maker said it expects to lose some sales to archrival Intel Corp.
Those chips, made by its ServerWorks unit, help business computers direct internal traffic. Their second-quarter sales accounted for about 20 percent of the company's $378 million in total revenue.
The stock fell $3, or 11 percent, to $23.53. That was its biggest drop since May 8, 2002, when it tumbled $5.22 after Motorola, one of Broadcom's biggest customers, decided to also buy chips from Texas Instruments.
Concerns about Intel overshadowed strong second-quarter results. Sales hit a record $378 million, and the company said it expects them to rise again in the current quarter, reaching $400 million to $410 million.
Investors are jittery because Broadcom shares have soared 50 percent over three months.
"People are concerned about ServerWorks," said Lehman Bros. analyst Arnab Chanda.
Broadcom chief executive Lanny Ross replaced the head of that business in March, citing production problems and differences between the two men.
Chanda said he thinks investors were focusing too much on ServerWorks and not enough on Broadcom's other businesses, which are growing.
His evaluation of the stock, after Wednesday's plunge: "buying opportunity."
Broadcom took a second-quarter charge of $439 million for impairment of goodwill on ServerWorks. That means the company has determined that ServerWorks is worth $439 million less than it previously estimated.
Intel, the world's biggest chip maker, recently introduced a product that competes with ServerWorks chips. Broadcom Chief Financial Officer Bill Ruehle said he expects Intel to "get more aggressive" and take sales away from Broadcom.
ServerWorks engineers are working on plans for new server chips that won't face competition from Intel, he said.
Fujitsu Siemens Computers PRIMERGY servers set the MMB2 standard
[Johannesburg, 24 July 2003] - In a recent series of MAPI (Messaging Benchmark) tests on an Exchange Server 2000 platform, the Fujitsu Siemens Computers PRIMERGY TX 600 four-way server showed competitors a clean pair of heels. Achieving 16 528 MMB2 users at a weighted 95th percentile response time of 136ms, the PRIMERGY TX 600 was equipped with four Intel Xeon MP Processors with 2.8GHz with 2MB L3 cache, 4 GB PC 2100 DDR-SDRAM and a total of 150 disks.
The MMB2 measures throughput in terms of a specific profile of user actions run over an eight-hour working day. This benchmark uses the "Medium User" setting of the Load Simulator MAPI tool and is meant to represent mail traffic from a typical corporate e-mail user, including common daily mail tasks such as sending, browsing, reading, and forwarding messages, in addition to scheduling tasks and using distribution lists. Results should be interpreted as a benchmark for messaging throughput and should not be confused with deployment recommendations.
The MMB2 test measures throughput in a single-server, single-site topology on this hardware configuration, and can provide a benchmark for comparing hardware or software products.
Beside this excellent result for a high-end four-way server, Fujitsu Siemens Computers PRIMERGY range of servers remain unbeaten in the category of two-way and one-way servers. In the dual processor class, the PRIMERGY RX300 shows the best MMB2 result for 32-bit Intel Xeon processors, with 11000 MMB2 users.
The mono processor system, the PRIMERGY TX150 achieved a class-leading 5400 MMB2 users.
Petz - Even at the chip level, the Itanium die size is twice as big, which means AT LEAST 2x higher silicon cost, since 374 mm is an extremely large area to have no Si defects, as Elmer has often explained.
It would be about 3.36x the cost, if they were running on the same process but a SOI wafer is more expensive, yields less and shows lower frequency as we have all seen. At 374mm2, if Intel has very good yields, they would probably see about 25 good Madison die per wafer. At $1800 per 8" wafer their die cost would be ~$72. Add packaging and test plus other misc charges and you wouldn't likely reach $125. That's IF Intel has very good yields. An Opteron sized die on the same process would probably have a total manufacturing cost of < $30.
I would guess that currently, Intel is getting more sellable Madison die per wafer from their mature .13u process than AMD is getting Opterons from theirs.
Tenchu - for SPECint2000, how is HP getting 1322 for a Madison 1.5 GHz, while SGI is only getting 1077?
I have no idea but I think wbmw had a partial explanation for this. Maybe he'll comment?
Intel Elects John L. Thornton to Its Board of Directors
SANTA CLARA, Calif., Jul 23, 2003 (BUSINESS WIRE) --
Intel Corporation announced that John L. Thornton, professor and director of global leadership at Tsinghua University in Beijing, was elected to Intel's board of directors, effective today.
Thornton retired July 1 as president and co-chief operating officer of Goldman Sachs Group Inc. and as a member of that firm's board of directors.
He is also a director of the Ford Motor Company, British Sky Broadcasting and Pacific Century Group Inc. He is chairman of the Brookings Institution Board of Trustees, a member of the Council on Foreign Relations, and a member of the advisory board or trustee of the Asia Society, The Goldman Sachs Foundation, The Hotchkiss School, Morehouse College, The Tsinghua University School of Economics and Management (Beijing), the Yale University Investment Committee and the Yale School of Management.
Thornton received a bachelor's degree in history from Harvard College in 1976, a bachelor's/master's degree in jurisprudence from Oxford University in 1978 and a master's degree in public and private management from the Yale School of Management in 1980. He and his family live in London and Far Hills, N.J.
"We are very pleased to have John Thornton join Intel's board of directors," said Intel Chairman Andrew S. Grove. "His background in management and finance and his 20 years of hands-on experience with international business will be immensely valuable to us."
Thornton's election to Intel's board brings the number of directors to 12. That number is expected to decrease to 11 in May when Charles E. Young, a director since 1974, reaches the board's mandatory retirement age.
I see there are new SPEC scores posted:
http://www.specbench.org/cpu2000/results/res2003q3/
The performance advantages of Itanium are even more dramatic. Other new x86 scores too.
wbmw - Did you write any CCs? The new $1 increments make it awfully appealing but you need a few shares to make the commissions a small fraction.
drjohn - This speaks volumes for Ruiz's disregard for his own shareholders, it makes it look like AMD management is their to milk the company for their own pockets kind of reminds me of the former CEO what’s his name.
And Hector is an improvement over what's his name...
AMD's Ruiz sees consolidation, slower growth in chip industry
FRANKFURT, Jul 23, 2003 (AFX-UK via COMTEX) --
Advanced Micro Devices Inc president and chief executive officer Hector Ruiz sees consolidation in the chip industry and slower growth than in the past, but does not expect that AMD will be the target of a takeover bid.
In an interview with weekly magazine WirtschaftsWoche, he said: "There will be a round of consolidation in the chip industry. We will have less providers and less growth in the future."
But AMD will continue to exist as an independent company, he added.
"We are like the American bullfrog. No one wants to swallow it, because it possesses a deadly poison. AMD also has such a poison: We compete with Intel," Ruiz said.
SZ - The usual Rackpro and Appro press releases were released but the two major design wins - Cray and Dan3 - seem to be the only end-sales so far besides some gratuitious Texas academic purchases of some cluster bomb Opterons.
Thanks for the laugh!!!
Petz - When it was released and through the end of June:
[numerous benchmarks listed]
This is revisionist history. All those SPEC scores were on unavailable hardware. The April SPEC scores were for hardware with July availability. By the time the AMD hardware is actually available Opteron loses every one of those benchmarks to P4/Xeon except for SPECfp_rate. AMD was boasting about 2.0GHz SPECint scores last year. They didn't deliver what they promised, just like I told you guys they wouldn't. AMD has had terrible yield problems just like I told you they were having. Face it, things have worked out exactly the way I told you they would.... But I'm not one to gloat...
Joe - If you are still in the business and virtually all but one of your competitors are out of that business, that's success.
Maybe by your measure but not by mine. Losing $billions$ while selling off almost every profitable division plus your headquarters building, and a share price that's below where it was 15-20 years ago is not a successful company in my book.
Haddock - I believe that discussion of moderation isn't wanted here
Actually I think it is wanted here. My only comment is in reply to the claim that Matt will restore posts he feels aren't a serious violation. The point is that the damage has already been done. No one goes back and searches for restored posts and they lose their relevence as time passes anyway. When you remove posts they are, for all intents and purposes, deleted.
I remember quite a discussion when I volunteered to be backup moderator. I don't remember any discussion about you. Did I miss something? Should the thread regulars has a say? BTW, I have no objections to you, I'm just questioning the process.