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Duke
I understand it so as well - if only to take the opportunity to say hello. Good to see you still around.
K.
Keith
ASPs are a function of the overall product mix sold in the quarter
Certainly. But the mix you depends not only on what the market absorbs, but from what you have.
AMD has inventory hopefully buffering the effect from low-feature inflow from Singapore. But they gotta do inventory management if they don't want to end up in Intels inventory situation. So I expect it will play into the equation for next quarter: Trying to put it in polite words: "Leaner" mix. Just to avoid poorer mix, you know. ;)
Not sure I made it easy to understand where I am getting at. I seem to be bad at such elaborations.
K.
Keith,
I would't deny it, although I guess reading over Gartner, IDC and Mercury delivers the most complete picture in color and shade - if you are aware where they count differently, that is.
With respect to Mercury's Q4-expectations, I'd expect AMDs ASP will be down again a tad, because silicon from Singapore plays into the equation with low feature-yields, from what I hear.
K.
Keith
figures feel pretty plausible with me, i mean within a ten percent error margin in each direction. Considering how difficult it is to collect solid data on what people pay one can't expect more precision.
K.
p.s.: Thanks for the warm welcome :)
OT Hi sgolds
Good to see you still around. Just curious, are you still running this restaurant? Or is it a restaurant chain in the meantime? :)
K.
Paul
I know. I was trying to subtly play ImageShack - imagesHack. Maybe I should have added "Pun intended", but I am not sure my licence of it covers outside-of-inq comments. :)
K.
Mike,
Couldn't the processor info added in v1.36 include "Brisnane"?
A real devil's advocat's argument, indeed: As long as nobody else has a Brisbane, nobody can prove you wrong. ;)
Got a good laugh from thinking it this way. :)
K.
Good to see you again, mate.
elmer
Good to see you got your two ducks in a row. :)
Smooth
I'd be the very last one to blame anybody for being puzzled with Intels Code-, brand- and CPU- names.
Because even in the times i tried to keep track I was puzzled often enough. Now, having been away from thread for a year or so, about the only I can identify without a notebook handy is "iNtel". :) And I do not intend to do anything against it.
K.
Smooth, disregard
Here is the revision history of CPU-Z:
Version Date News and corrections
1.38 11/22/2006
* VIA P4M890 and P4M900 chipsets.
* NVIDIA 650i and 680i chipset.
* AMD Athlon 64 FX-7x processor.
* Core 2 Duo E6850, E6750, E6650 processors.
* Socket 775 Xeon processor.
* New parameters "-txt" and "-html" (see above for more details).
1.37 10/02/2006
* New HTML report.
* Intel Core 2 Quad, Celeron 360, Mobile Core 2 Duo T5200 support.
* Added VIA VT8237A southbridge.
1.36 08/18/2006
* New processor information display.
* Intel 5000X/P/Z/V SPD support.
* Intel Pentium D 925 & 945.
* AMD K8 family HyperTransport link speed.
1.35 06/27/2006
* ATI RS350, RS400, RS480/RX480, RS482, RD580/RX580, RS600/RD600, RS690, RS700 chipsets support.
* ATI SB600 southbridge support.
* Intel P965 chipset support.
* Engineering samples Core based CPUs report.
* Windows Vista product line report.
The poster did not even bother to fake a Version which theoretically could be aware of Brisbane.
Even faking degenerates nowadays, apparently
K.
Smooth,
does CPU-Z has a version out to display Brisbane already?
K.
p.s: Good to see another old buddy again. :)
elmer
I would not know of any credible source who touched one either. But I am pretty sure there is working samples at AMD.
There is things like http://img377.imageshack.us/img377/8012/bris01vt5.jpg posted, but a site with the name imageshack is certainly nothing I would build anything on.
Long story short, I am the very last to dispute a paper launch. In fact, I do not remember to have seen one as obvious as this one. So let's just call a duck a duck and we are done with it instead of looping into a discussion whether it is fully debugged yet or how long the list of known bugs might still be.
K.
elmer
No, I mean any fully functional 65nm product.
If you are referring to the products they announced - they have one of each of these, I guess. Maybe even a handful ;) Although these do not seem to be completely in 65nm geometry yet, if I understand it right.
K.
wbmw
Don't people usually call events like these "vapor" launches?
It has many names - from different angles. In financing facilities referred to as "milestone", e.g. ;)
K.
elmer
Nope. They just met my expectations I had since they disclosed what they will do in Dresden couple years back. See e.g. http://www.investorshub.com/boards/read_msg.asp?message_id=6771785
As for "fully functional 65nm product" I assume you mean quad with all bells and whistles on? If so, I think it would be insane to hold your breath for it. Something to show by mid next year, volume by end of next year is rather on the optimistic side, imo.
K.
mas
C'mon. There is plenty 65nm product out there. Even yields look great already:
http://akiba.ascii24.com/akiba/news/2006/12/07/images/images827547.jpg
K.
Chipguy
Interesting. Many thanks for elaborating on it. There is probably many more things I missed while having been away from the thread for quite a while.
While we are at it, is Carbon-Nanotube still considered as a possible candidate down the road?
K.
wbmw
I stumbled over this tidbit:
nine copper and one aluminum metal levels
Al and Cu in the same fab is not exactly what you want in the first place. There might be compelling reasons to do it anyway.
Besides, the layout of the Dresden facility allows such an approach probably better than most other fabs would.
K.
On a sidenote, I like the idea of this board.
Third, wrt Prescott, rumours Intel will introduce T-technologies on 90nm products indicate Prescott's circuitry is still not completely utilized in current products. Although this is still rumour afaik. (?)
Not confirmed yet, but a thickening plot, here: http://www.theregister.com/2005/10/27/intel_p4_vt_launch/
K.
Joe
It's kind of like the Special Olympics for Xeon only
Paralympics you mean, I guess?
K.
Joe
I hear you, Joe:) I already accknowlegded Wouter Tinus' take and arguments (to look at Yonah as just a marketed development vehicle for Merom) have merits. Insofar, my level of conviction Intel does what it ever did is lower after this thread than at its beginning. Actually both assessments could be right indeed, as well: Merom (and Conroe) derived from Yonah die still fabbed for the rest of the node, but relegated to valuespace over time, the Merom/Conroe versions derived from Woodcrest(Server)-die for Desktop and mobile performance, beginning with EE and then penetrating performance segments from the top. In fact, I am currently leaning towards this stance.
K.
jj
Many thanks for providing the sortable version to us, and to Mike for delivering data.
Pick up of Dual Core is impressive: X2 3800+ with a five digit figure currently having highest order volume of all AMD products is remarkable. Clearly, AMD significantly widened its access of buyers spending over 300 bucks for a CPU.
In essence, looking at these data sequentially does really help to understand transitions better imo. (This weeks data is reason to adjust Dual-Core numbers for me). Btw, I remember you considered grafical analysis of data at some point. I think it could be helpful to further aggregate and visualize the valuable content.
K.
wmbw
Which products are fabbed on the 130nm/300mm combination in Fab20 and Fab 22?
K.
wmbw
- Hillsboro, Oregon, fab 20, 130nm
- Chandler, Arizona, fab 22, 130nm
Are you sure these are 300mm??
K.
Rupert
BtB acutally should be just a simple ratio of what has been taken on orderbooks and what was sold in revenue terms. However, first they cautioned they might not be able to supply it, and second they don't say anything about lead times of the orders taken.
K.
Keith
Manufacturing capacity constraints may adversely affect us.
Lol. It's a form and content play, subtly transporting the message they need equity to skim the cream of growth, iaw suggesting a plausible reason for the IPO. Nicely done. :)
K.
WT
You put question marks behind everything Intel says
Sure. If you listened to them in the recent couple years, you know there is any reason to do so, imo. Btw my questionmarks are not exclusively reserved for Intels balloons.
Anyway, I'll ask them next week for more details, but I doubt they can give me anything new to share.
Good luck. :) There is not many at Intel who actually know what you want to learn. Keep us informed of what they say please.
K.
Alan
many thanks. Not confusing at all, fully consistent with what the article says as well.
K.
Keith
An excess supply of Intel processors purchased this summer ... could lead to price cuts of as much as 10 percent on computers over the next three months.
Well now that sheds some light on Intels Q3 revenues and meager outlook for Q4.
K.
Keith
Suggest to listen into the Chartered Call, in particular to Sunil Guptas q (mediaplayer timestamp 1:30:30) to get a better idea of how to understand this. In another statement earlier in the q&a Chia Song said Chartered does not utilize strains in their 90nm node btw. (Did not note the time stamp for this one.)
K.
WT
I'm not sure what else to make of this, but perhaps you can spot something interesting :).
I'm reluctant to draw any conclusions from these kind of portrayals. Whenever Intel publishes such, it usually has a footnote somewhere saying graphic not representative of actual die photo or relative size, but which gets lost when posted elsewhere.
Do you know of a case where only active transistors were specified? They didn't do that when they announced Prescott and pretended it was 32-bit only. I remember everyone saying that there were 'too many' transistors on that core.
First, nobody can count the transistors. Second, Intel is not obliged to use transistorcount-figures coherently. Third, wrt Prescott, rumours Intel will introduce T-technologies on 90nm products indicate Prescott's circuitry is still not completely utilized in current products. Although this is still rumour afaik. (?)
K.
Alan
Thanks. Links work now. It's the pictures I have seen, actually I believe Charly was smart enough to put his phone next to the packages for reference when photographing for an inq-article.
K.
WT
Ok, I like your style, to begin with.
I think given the transistor count that is not possible. Yonah has 151.6 million transistors, only 11.6 million more than Dothan with the same amount of cache. And they have to put a whole second core in there ;). I can see how they can do that with a little optimization in the caches here and there, but not while also packing both cores with a ton of new features at the same time.
Good approach, imo. Two suggestions to follow on it:
1. Take Dothans and Yonah's diesizes into account.
2. You will hardly catch Intel with a lie. You can believe what they say. But you should always have Andy Grove's "only the paranoid survive" in mind when listening to what they say. In this case, they say Yonah has soandsomuch transistors. They don't say whether it is the physical transistors on the die or the transistors used for this particular product.
I believe your assessment has quite some support in what I hear out there. Mine is actually primarily based on the paradigm that i always have seen Intel doing what makes most money for them, and will likely continue to do so. But they might indeed feel the need to offer more than couple hundred million marketing campaign to hold the fort anytime soon and throw a billion or two on manufacturing next year.
K.
Alan
Thanks for the pointer. While your links produce 404 here, I believe to have seen the photos. However, slide 13 in Wouter's link shows two versions of Conroe-dies.
Apart from this, Wouters and I talk about Merom and Yonah anyway, not about Conroe. But then, Mooly said in Asia Intel will bring the larger die into mobile space as well. Beyond, just to be halfway complete, the larger die has lower feature-yields as well which Intel wants to sell, so there certainly will be larger die products specced like fullfeatured smaller dies. Semiconductor-economies can be confusing. :)
K.
WT
but I'm willing to redefine the topic of discussion to the core, if you are ;)
I am this flexible, to begin with :)
In terms of silicon and core-design, a new silicon-spin is always an opportunity to integrate and optimize things you were not able to fix at stepping-levels even if we are talking about a shrink only or changes of Cachesizes - insofar the two topics are not completely independent.
In this particular case, one of the crucial points of the 4MB L2 parts will be the decision for shared or exclusive Cache(s). e.g. :)
Are you somewhat suggesting we should look at Yonah as the folk group entertaining the enemy until the troups arrive? :)
K.
W T
Or that Yonah is also part of this Next Generation Micro-Architecture?
Yes. Just not with all features of it. Which comes back to where we started the exchange.
What you say in your last paragraph is a possibility. While the one I suggested would certainly be far superior for Intel from an economic viewpoint, there is indeed a possibility that it simply was not ready in time for tapeout when Intel had to start process development and therefore had to use a former designpoint for a bridging product.
Well, it's an AMD board, so I think it is appropriate to let this spin of it stand juxtaposition to mine. :)
K.
Wouter Tinus
As the digitimes Article cites recent Intel-statements as well, this excerpt needs an addenum to my previous posting:
Compared to Yonah, it will have a larger level-two cache (presumably up to 4MB) and will contain some micro-architecture innovations, according to Eden. One of these innovations will be a higher performance 4-issue out-of-order engine with deeper buffers and a pipeline extended to 14 stages
The 4MB part of it applies indeed to different Silicon, which previously has only been communicated for Woodcrest and Conroe (Top-End). Apparently Intel recently chose to bring it to mobile performance as well. Centrino EE, anyone? :)
K.
Wouter Tinus
Many thanks for posting this list and links.
For obvious reasons i don't comment on what second sources speculate but strictly base commentary on what Intel says, i.e. in the IDF slides.
Intel says all what you post. But it explicitely attributes these features to "Intels Next Generation Micro-Architecure**" and are well covered by the footnotes on slides 9, 10 and 13 for anybody making anything else out of it.
On the pipeline thing, current Pentium-M is Dothan, not Yonah.
The 32-bit to 64-bit transition alone already makes it a new core.
This would imply your premise EMT64 needed new silicon as well, am I right?
K.
Jules
Tad LaFountain brought this very argument up a year ago publicly, although not in the concise eloquence necessary for many to get a grip at where exactly he was getting at, in fact it unfortunately sounded like lamento for most.
But well. Opportunism beats original analysis, as usual.
K.
wmbw
They did a slide of this at last IDF. You can probably do the research better than Wouter. Try Anandtech, I think I remember them showing something on it.
While homeworks is apparently not a particular strength on your side, it's premature to blame Wouter being not able to do it imo. At least it is easy for him to come up with more than a vague remembering of an IDF slide you have to offer.
K.