Advanced Micro Devices Inc (AMD)

[kpf]

WT

but I'm willing to redefine the topic of discussion to the core, if you are ;)

I am this flexible, to begin with :)

In terms of silicon and core-design, a new silicon-spin is always an opportunity to integrate and optimize things you were not able to fix at stepping-levels even if we are talking about a shrink only or changes of Cachesizes - insofar the two topics are not completely independent.
In this particular case, one of the crucial points of the 4MB L2 parts will be the decision for shared or exclusive Cache(s). e.g. :)

Are you somewhat suggesting we should look at Yonah as the folk group entertaining the enemy until the troups arrive? :)

K.