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OT Elmer
Now you' ve made it over the top of my head. What does "mismay" mean?
Tx
K.
chipguy
Not sure why you take over. I thought Elmer was only suspended from si.
A pity. I liked his more subtle posts.
K.
Windsock
Now I fee really at home, returning after a year or so. Not even these old socks in the corner have been removed since I left. :)
K.
Elmer
That was purely hypothetical but I'm glad to see that you accept the metaphor of AMD as thief.
Oh my. AMD is plaintiff in the Case, Intel defendant. If a thief can accuse the one he tried to steal the wallet in U.S. law, what people say about America seems to be true: Everything is possible. :)
K.
elmer
It is not a reasonable settlement to give him half your money.
Duuh. This would be about eight billion USD if memory serves wrt Intels pockets. You think it could end that bad? :)
K.
elmer
If a robber was trying to steal your wallet would you consider a settlement reasonable?
No. If Intel would have done it as humble as this it would have been sentenced already, without much ado. :)
K.
Smooth
Looks pretty similar from my stance. However, judges usually try to lead such cases to a settlement. Reasonably so, imo.
K.
Keith
Another Mosesmann.
No. Hans in unique. He left Moors and Cabbot and signed in to Nollenberger. Different firm, same call.
K.
elmer
Naah.
Light is just the association every Core-designer at Intel would likely produce when looking at the Barcelona-Concept. From there to K8L it takes only a nanosecond. The joke he makes of it spreads like wildfire in the company as jokes about the competition always do. Reaching PR. Charly calls in. Neither of the latter has even the slightest clue what the joke really is about, as usual. Charly is breaking the news. So it goes.
K.
Comb
I did not know this. It makes complete sense in any respect.
So I can take this process from the batch. Thanks.
K.
Many tx again, Mike.
Looks like a footprint of Henri's shoesize and profile. Good to see another quarter of excellence in channel management.
K.
Many thanks Mike
VERY noticeable improvement in AMD 64 and X2's this week....in availability is what you get at, i guess?
Aside from numbers, how did the market feel for you this quarter with respect to deliberate tight grip on supply versus factually short supply?
K.
elmer
Don't worry, I understood your message initially as you clarified it. :)
K.
elmer
This is something that needs further processing. I do not want to believe it is that easy and am inclined to argue against it - but what you say feels not wrong.
K.
wbmw
I believe this is the supposed stepping that will physically chop the 2M of unused L2 cache, reducing the die from ~145mm^2 to ~110mm^2.
Now that you say it i remeber to have seen mentioned reduced diesize for manufacturability when i flew over it. Thought it would be only the usual smaller adjustments in the single digits improvements i have seen often over the nodes in steppings.
It could very well be what you think. I did not know it was supposed to process a 2M-L2-layout. If so, they must have excellent cache-feature-yields. Bringing 4M-versions to the desktop indeed suggests so, as well.
Not that they would not have any issues, though. Justin Rattner did not sound overall happy with 65nm. But cache seems to be chipper.
K.
BobW
"Lehman Brothers, which thinks that AMD is capacity-constrained, also thinks that Intel may be aggressively pricing products and quotes China-based Commercial Times, which cites PC OEMs as its sources, as saying that Intel may again cut prices on its P4s by better than 60% on January 21."
http://br.sys-con.com/read/315235.htm Tx tecate for digging it up.
So far for this part of your take, which I agree in. As for the Barcelona generation doing anything good for AMDs ASP, i doubt it will. Actually the design looks like its name, i mean K8L. I look at it as K8 Light, if only to avoid the worn-out Late and Little cliché, although it might fit as well.
But well, maybe an opportunistic strategy seeking AMDs hail in valuespace for couple years is their best option. As always, time will tell. For now, right or wrong, while i like the atmosphere in the little restaurants around Ramblas, i don't like AMDs vision of Barcelona.
K.
OT elmer
Actually I didn't. I changed it just before the posting to tecate. But I realize ihub-system did change it for all of my postings I ever made.
Well. So be it.
K.
tecate
...as saying that Intel may again cut prices on its P4s by better than 60% on January 21....
Duuh. Max the Axe.
Actually, i post just to see my new sig under a posting. What do you think? :)
K.
golfburn
with wear leveling the robson card should outlast any notebook i've ever owned.
Possibly. The notebook won't stop to work when Robson's ASIC eventually considers every cell as unusable. ;)
Fun aside, i am fully aware everything in a notebook has a limited life. For the one i use now I needed a inverter replacement after 18 month (on warranty), couple month later a new optical drive, a new battery. And a new keyboard, but this was beause i left it open outside for long enough the asian midday-sun deformed some keys. :(
So it's obviously an emotional matter that I do not want solid-state memory with a limited lifetime in my notebook.
However, i trust this system more than any of my conscious considerations.
K.
p.s: Reminds me I should change sig. Had this one for long enough now.
wmbm
Gee. Intel is fast.... Hats off.
They have a PCN out today, exerpts:
Intel® is initiating a B-2 to L-2 stepping conversion for Intel® Core™2 Duo processors E6300 & E6400 (Conroe)
CPUID will change from 6F6 to 6F2
Extended HALT power specification will reduce from 22 Watts to 12 Watts
For details refer to PCN 106853-00. No Spec-update out, as far as I see.
K.
Robson
Did not look closer at use in operation yet, it's way more complex there.
...sigh, but could not resist to dig into it.
What I found is Robson leverages a feature of vista to use additional memory devices. I missed this because Knut does not even mention this in his presentation. As I understand it seems to be capable to assign its virtual memory across multiple devices, i.e. on HD and a flash-device. If it is capable to read from both devices simultaneously and writes large things to HD and small things to Flash performance would benefit from high data transfer rate of HD and fast accesstimes of NAND.
Robson seems not to be a layer between RAM and HD, but in the same hierarchy level of HD, if i got it right.
The Vista-feature does work with USB-flash stick as well, and with Hybrid Disks. So what Robson seems to add to Microsofts technology is its wear-off leveling management (not sure hybrid-disks have it as well).
Bottom line, this thing offers a proposition. However its implementation would make a lot more sense in a form-factor of a memory-card with wear-leveling asic on chip. You don't even need to throw it away when Window recommends you to replace it. It is still good for storing data on it.
K.
alan
I have data now from Intel for Flash used in Robson
40Mb/s write, 12-15Mb/s write
I updated me on harddisk sustained-data-rates, these did not change much within the last year: 40 MB/s. This is for a slow notebook-drive at 4200 rpm. Thought this would be appropriate for a comparison.
It's still what came out last time i looked at it, for suspend. Unless you point me to an error, that is.
Did not look closer at use in operation yet, it's way more complex there.
K.
gb
was curious what intel would say on direct questions wrt availability of Robson and flash specs. Here is:
"Robson technology will be available on Intel’s forthcoming Santa Rosa platform....
...long rah rah....
...still rah rah...
Systems with Santa Rosa and Robson technology are expected to launch in the first half of 2007.
I guess you know how to translate this.
And on the management thingie we talked about, and on flash specs:
Robson Technology Architecture
Robson technology consists of four components:
* Robson driver. This is the heart of Robson technology—the Robson driver interfaces to Microsoft Vista’s ReadyDrive and ReadyBoost technologies, interfaces to the Intel® Matrix Storage Manager driver, and provides all the control functions necessary for managing NAND flash in a caching role.
* Intel® NAND flash memory. Robson cards are powered by Intel NAND memory that offers 40 Mb/s reads and 12-15 Mb/s writes.
* Diamond Lake ASIC controller. This controller translates the system’s PCI Express signals to the Intel NAND memory and manages the retirement of Flash memory blocks as needed.
* OROM BIOS. Robson technology includes BIOS-level option ROM (OROM) code which manages NAND access before the OS and drivers load. The OROM also controls separation handling, critical to maintaining data integrity.
K.
wbmw
You heard this where?
From a Chipbroker in Taipeh. Couple 100K to Red China, he said.
Why would volumes not taken by Dell be further discounted?
Not further discounted, but sold to (r)etail for less discounts than Dells rebates. If Dells rebates are say 50% to list, and they can sell to etail for 40% under list, you'll see them offering the parts for 30% under list. Just exemplaric, I don't have current data. But it should be about the ballpark. That is why you see most discounts on high priced products in etail. These are hard to sell for reasonable prices in China.
K.
Ronster
Don't worry. Keeping track of acronyms, codenamery and product names of various companies binds too many memory ressources. There is better use for these.
K.
p.s: Thanks chipguy.
wbmw
With all this discounting, what will be the affect on AMD's ASPs?
Assuming the reason for the discounts is volume not taken by Dell and further assuming Dells rebates are higher than what you see in etail, the effect is rather up than down for this Q.
Going forward, it's probably just an anticipation of the price-round which traditionally happens in early January. Henri has demonstrated tight grip on channel prices since years. I don't think he would allow discounts to become visible beyond planned price-cuts in the very near future. I've neither seen him flooding channels by q end nor floods from OEMs to the retail for long. AMDs "asian affairs" seem to be resolved as well.
Otoh, most of the volume Dell didn't take went to China, from what I hear. And these chaps don't pay much either. Maybe even a tad less than Dell pays for volume they don't need desperately.
Hard to say what the overall effect for the Quarter is. I don't change anything.
K.
Keith
Occasionally it works pretty well. I doubt AMD would still exist without it. I am referring to the case that led to the settlement back in 1991.
K.
tecate
Don't you worry sweetheart.
It's just a recommendation to consider alien documents, so far.
No ruling yet - due Jan 12th earliest, and only to this point.
Enjoy your evening.
K.
Chipguy,
before I google this out, what stands NGMA for?
K.
wbmw
Well now, with all due respect that you said it in your previous post does not prove it right, does it?
I have no transistorcounts at hand for present MPUs, but it would surprise me if Intel needs more than twice the logic transistors to compete with AMD. At least they did a lot better for all the time I followed their archs. ;)
K.
wmbw
Actually, I said that Core 2 had >2x as many LOGIC transistors...
U sure, mate?
K.
wbmw
Since we already know that Core 2 has more transistors (more than double the number of power hungry logic transistors), so this is not all that surprising.
Yes. I think it is really that simple. That is exactly (and only) what I was getting at.
Tx for your calculations. This is the data i referred to when I said it must have been a product where SRAM is not sent to sleep in idle operation, which you confirmed in a previous post for desktop products.
K.
gb
Forster River is not a chip, but a card containing flash and periphery for Robson. Guess it is the best way to implement it this way.
K.
wmbw
In AMDs PR there is a comparison of Brisbane to a Product from Intel wrt idle power, but not more specific as its TDP is at 65 Centigrade.
The SRAM cells themselves can go to sleep when not in use, dissipating almost zero power at that point.
I know this is the case for notebookprocessors. Maybe I missed this is implemented in Desktop nowadays. But the data I see do not indicate this.
K.
p.s: Apologies for confusion. I am answering phone calls in german while typing, so grammar might get mixed here and there.
gb
that it is unclear how the other approaches will handle. this enhanced wear leveling algorithm was mentioned by grimsrud in his presentation.
The management is probably on Forster River, then. Which, as I said, adds overhead to consider.
K.
wmbw
Certainly. I did not say all it used for cache, but the most. And this is, as you kindly elaborated it on ausführlich, where the most transistors are.
Btw what name has the 65W-point product from Intel AMD compared its Brisbane to and how many cache is used in there?
K.
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