Intel Corp (INTC)

[kpf]

wbmw

I believe this is the supposed stepping that will physically chop the 2M of unused L2 cache, reducing the die from ~145mm^2 to ~110mm^2.

Now that you say it i remeber to have seen mentioned reduced diesize for manufacturability when i flew over it. Thought it would be only the usual smaller adjustments in the single digits improvements i have seen often over the nodes in steppings.

It could very well be what you think. I did not know it was supposed to process a 2M-L2-layout. If so, they must have excellent cache-feature-yields. Bringing 4M-versions to the desktop indeed suggests so, as well.

Not that they would not have any issues, though. Justin Rattner did not sound overall happy with 65nm. But cache seems to be chipper.

K.