Replies to post #3002 on Advanced Micro Devices Inc (AMD)

[Elmer Phud]

Tench -

I doubt the memory request is speculatively issued on every access to L2. That would create way too many bus requests that would later need to be cancelled, especially when you're talking about L2 hit rates of 95%.

So how do the other processors snoop the address otherwise?

[j3pflynn]

Tenchu, I was actually referring to the physical differences between the caches that allow Intel's to be smaller per unit of memory, and whatever other physical differences. I was already aware of the inclusive/exclusive difference.
Paul