Replies to post #1560 on Advanced Micro Devices Inc (AMD)

[Elmer Phud]

Yourbankruptcy -

You are missing an obvious disadvantage of the Opteron architecture. Snooping requires a hop for Opteron and a hop to wait for a response. On a shared bus each processor sees the bus activity in real time with no hops. Additionally aHT has no ECC. It relies on a CRC at the end of every packet. This, along with the snoop hops cuts into bandwidth. I think you have bought into the hype when there is no data whatsoever to support your unbounded optimism.

BTW, it has been suggested we use the terms aHT to refer to HyperTransport, and iHT to refer to HyperThreading. It think it's a good idea.

[chipguy]

So, 4-way Opteron works practically as a single chip with 4 cores on die.

Practically? I guess if you don't mind adding four chip crossings/retiming/rebuffering
worth of delays to implement coherency to memory accesses, then I guess it works
*practically* as a single 4 way CMP chip. A really badly designed one, that is.

[Tenchu]

Yourbankruptcy, I was looking for actual benchmarks, not theoretical discussions of architecture. Dan3 tried, but as usual, he purposely pointed to programs that weren't supposed to run fast on Itanium (i.e. 32-bit programs running in emulation mode).

<4-way Opteron works practically as a single chip with 4 cores on die.>

Uh, no. For Opteron, every memory access must be snooped (or probed in AMD terminology) by all other processors in the system. Thanks to the ring structure of the HT links, this broadcast ensures that every memory access has the latency of at least four hops (two to go to the furthest processor, two to return).

Face it, the latency increases with every processor added to an Opteron system. Of course, Opteron will make up for this deficiency in added bandwidth per processor, but that's far from claiming this is equivalent to a quad-core chip.

In other words, I see nothing but a "logical" argument based on wacky assumptions. Nothing is new under the sun.

Tenchu