Replies to post #4784 on Rambus (RMBS)

[cordob]

Hey Elixe

I am sticking to my 8 bytes (i.e. 64 bits) granularity on this.
Don't understand the problem.

We need a 64 bit wide bus to get a total bandwidth of 800MBps.
(your spec)

Granularity by definition is the smallest unit of data which can be extracted from the memory, so to get that I have to use a burst of 1. Prefetch is also 1 for sdram (i.e. does not exist).
So at a burst of 1 I get 64 bits, which is the granularity. Longer bursts cause one to get twice, four times etc the granularity.

Btw, quite another point, now that the prefetch is often 4 bits and up on various memory chips, programmed bursts lose their usefulness. One simply has to issue subsequent reads (one NOP inserted) to keep streaming the data. This does not affect the bandwidth as on DDRx it is a pin at which it is asserted and on XDR it goes on the command channel.

So one of the four main infringement aspects of DDRx goes away. Dual edged clocking was not accepted in the hynix case (correctly, because it is a different type of clocking than that in the patents). The main thing is still the latency register.

Cheers
Cor

[calbiker]

Re. Why don’t you answer the question?

Is this a new tack of yours? Before you were adamant that:

Granularity = Bus Width * Prefetch

Are you now saying you were wrong?

Does burst length have any relevance in your equation?

Have you gone off the deep end? Or are you strategically changing topics to save a little face?