Replies to post #41822 on Advanced Micro Devices Inc (AMD)

[wbmw]

Grimes, the best I could find was the latency to enter grant state, which is 20 bus cycles:

http://www.intel.com/design/xeon/datashts/30235501.pdf (page 76)

It doesn't give much information on SpeedStep latency, but I imagine there is some delay required to get the PLLs to latch onto a new multiplier. Grant state simply turns the clock off until one of a certain number of interface signals are polled. A 20 cycle delay on an 800MT/s FSB is only 25ns. Therefore, it may take more time to get out of stop grant.