Replies to post #79717 on Intel Corp (INTC)

[joseph pareti]

cool post

[tecate]

I agree with the poster who said 'cool post' but I would add that perhaps some of AMD's problem is their inability to retain good, experienced designers, with the sword of damocles hanging over your head, who stays on that ship??

your post was very informative, thanks.

tekate

[subzero]

"I don't think they have depth on their engineering players bench to take on this huge challenge.

AMD's public disclosure yesterday of their Server roadmap is an admission of this.

They seem to have the ability to take that old K7 core and "step and repeat it" across a layout, hook them up to each other and external L3 cache - to yield ever larger multicore K7 die.

Period.

As you say, to get a product to market, in a reasonable time frame, that is all that AMD seems capable of these days.

AMD seems to have abandoned any hope of adding Simultaneous Multithreading to their core architecture and rather than have a five year effort with a group of architects and designers dedicated to a "clean sheet" redesign, AMD seems to be cornered into a an ALL HANDS ON DECK situation where everybody is focused on getting a 'K7 times n' product to market as quickly as possible to prevent AMD from becoming technologically irrelevant, let alone technological leadership.

I guess that happens when there are no more ideas to steal from the now long defunct Digital Equipment Corporation.

AMD also seems to have reached the conclusion that lawyers are easier to hire than experienced microprocessor professionals.

[smooth2o]

That's a great post. I would add that IMO AMD did have a design however that design was so inferior to Intel's present offers that they must have had to scrap the design. I say this b/c I can't believe that they could not have been working on something or that would have consumed their design resources. Just a guess.

Smooth

[wbmw]

Chipguy, here's what I think is interesting.

Shanghai has multiple flavors, found here:

http://products.amd.com/en-us/opteroncpuresult.aspx?f1=Third-Generation+AMD+Opteron%e2%84%a2&f2=&f3=&f4=512&f5=Socket+F+(1207)&f6=C2&f7=45nm+SOI&f8=&f9=&f10=4&f11=&

In terms of peak frequency at each power level, the stack looks like this:

105W ACP (137W TDP) - 3.1GHz
75W ACP (115W TDP)- 2.9GHz
55W ACP (79W TDP) - 2.5GHz
40W ACP (?? TDP) - 2.3GHz

This is with 4 cores, yet on the same process node, they expect to ship 12 core products. What will they be able to hit in frequency, just to have reasonable power limits? Even assuming the lowest voltage part above, once 3x the cores are assumed, it ends up with power greater than the SE-series power envelope today.

They will need to have rather aggressive voltage scaling and meager frequencies, just to get Magny Cours out the door. That's not an elegant solution, but I'm sure Intel is flattered that AMD is copying their MCP approach, now that Intel has moved to "native". :-)

[rudedog]

Thanks for a very enlightening post, even if much of it went over my head. Are there any simple process enhancements to that base AMD design that could make a dramatic improvement in the power profile? It seems like getting to a much lower power part will be important to maintain any profile in mobile.