InvestorsHub Logo
icon url

dacaw

06/14/04 5:30 PM

#37976 RE: DDB #37968

"dual core test wafers went through the fab already several weeks ago"

Well, said with a confident air, like someone who was there?

So you're saying - correct me if I'm wrong - that the tapeout was completed and the test batch passed muster? That was the reason for the PR piece?

So the next step would be twiddling the masks to optimize speed & yield?

Sorry for so many questions. Your post was short enough to be enigmatic. Just a generic overview of the necessary steps - and where AMD could fall behind if something goes wrong - would be more than welcome.

Thanks DDB
icon url

jhalada

06/14/04 6:56 PM

#37985 RE: DDB #37968

DDB,

That means tapeout must have happened some time ago.

BTW, I can't help but be a little underwhelmed by AMD's dual core schedule, based on the fact that all the hard design work happened back in 2000 or so, the implementation of most of these hard issues (System request queue, crossbar) is already in all shipping Hammers.

I was expecting dual core Hammers sooner, as soon as 90nm yield is satisfactory = Q4 2004.

Joe
icon url

j3pflynn

06/14/04 9:28 PM

#38001 RE: DDB #37968

DDB - :-)