Replies to post #35169 on Advanced Micro Devices Inc (AMD)

[Petz]

I wonder if AMD's cache design and cache coherency architecture fully exploits the knowledge about the way memory pages are "marked." For example, if a page is marked as "no write," then a CPU doesn't have to do any snoops to find a newer copy in someone else's L2.

Petz

[UpNDown]

jhalada, on trace cache for K9

What is it about trace cache that you consider worthwhile? Why bother with it? AMD has a perfectly competent instruction decoder in the pipeline and instructions can be selected differently for bundle packing each time through, depending on register dependencies or memory-access latencies. Those advantages would be lost (or at least misplaced :)) with a trace cache, wouldn't they?

Everybody thinks x86 is terrible and has to be fixed. But once the logic has been worked out, it's not bad at all. I like to think of an x86 instruction code sequence as a compressed code sequence. Really, that's what it is. With not so many 8-bit operations being used now-a-days, the compression isn't optimal, but it suffices.

Think of your typical risc operating code sequence, then make the following changes:

- compress it so that more-used instruction sequences (say, add from memory) are shorter

- tailor the compression so that it uses byte-length operations only -- for ease in the decoder

and what do you get? Something similar to x86. Now, it's bloated somewhat over the years, but that's the cost of backwards compatibility, and we're gladly paying it.

[Grimes]

jhalada, what is trace cache? (TIA eom)