Replies to post #53465 on Intel Corp (INTC)

[kpf]

So most likely AMD will stick to 65nm transistors, and shrink the other features only
This is a peculiar idea. :-)

K.

[fingolfen]

However without HiK, you cannot shrink the 65nm transistors any further,without a dramatic increase in power. So most likely AMD will stick to 65nm transistors, and shrink the other features only. So there will not be any performance gain, and the chip size will not scale as normal shrinks do.All the SOI gains have been accomplished at earlier nodes, so it is unlikely that AMD can pull anything new out of SOI hat.

I agree and disagree with you here. You can shrink the transistors, but you may not be able to scale the gate dielectric. That will sharply limit the benefit of scaling the transistors (in terms of increased speed and reduced power).

Basically I see AMD shrinking the transistors to 45nm node gate lengths, but unless they adopt high-k, they won't be able to scale the gate dielectric. This means while they'll gain compaction advantages from the 45nm node, the performance pop will be modest at best.