Replies to post #19762 on Advanced Micro Devices Inc (AMD)

[blauboad]

The slide is talking about RAMP comparisons. That strongly implies that time also increases as you move from left to right, since any decrease in volume indicates the end of the ramp, so data from that point on is probably not shown.

I'll buy that. I was hoping AMD might have inadvertantly released evidence of demand-constraint. *sigh*

Though as I think Alan pointed out, the use of volume instead of time makes the 130nm SOI line much steeper and shorter than it would otherwise be. All in all, yield improvements probably have occurred on par with the other processes, which is good news I'd say. Now, I don't know a damn thing about it, but I wouldn't think that huge volumes would make it any easier to get better yields, whereas lots of time should.

[jhalada]

doug,

I have to agree with chipguy on this one. You can make the curve in AMD graph arbitrarily steep by slowing down the ramp of wafer starts. One information you can take out of the graph is that the slow ramp enabled AMD not to waste too many wavers while the process was low yielding.

Also, since the "mature yield" is in the eye of the beholder, we don't really know what it is and how it compares to Athlon. Does the "mature yield" correct for the difference in the die size? We don't know. If the number is an absolute threshold of % good die, than the news is very good. If the "mature yield" is not a % of good die, but something that takes die size into consideration, and is more related to defect density, then we don't really know much from it.

Joe