InvestorsHub Logo
icon url

Not a Short

12/01/03 12:25 AM

#19046 RE: Dan3 #19026

"Look at the left hand slide on the bottom of page one. It clearly states that Instruction 1, Instruction 2, and Instruction 3 are loaded each clock.

These instructions are independent of each other and are not micro-ops. Itanium functions as a triple core CPU.

Take a look at the example at the top of the next page: it shows a typical operation where one core is performing an add, the second is performing a subtract, and the third is doing a shift."


except one tiny detail, you are misusing the word "core". yes the modern CPU can do more than one instruction in parallel but that doesn't make it multi core. Imagine the 8088 for a second. If there was an instruction that took more than one cycle to complete does that mean it was a 1/3 core cpu? the x86 cpus before the 486 didn't have a math coprocessor built in so was the 486 a 2 core cpu?

How about this. Just go to http://www.geek.com/news/geeknews/2003Feb/bch20030214018671.htm and read the article. It's less than a year old and has tidbits like Single-core speed will level off around 5GHz, and we'll begin moving to multiple cores and specialized parallel computing to achieve greater throughput.

I haven't seen any 5 GHz or better Itaniums lately and if I did I'd crap my pants worrying about my AMD stock.

Seriously read that article and all the replies to it and see if you can catch what the rest of the world means by "cpu core".