Advanced Micro Devices Inc (AMD)

[Dan3]

Look at the left hand slide on the bottom of page one. It clearly states that Instruction 1, Instruction 2, and Instruction 3 are loaded each clock.

These instructions are independent of each other and are not micro-ops. Itanium functions as a triple core CPU.

Take a look at the example at the top of the next page: it shows a typical operation where one core is performing an add, the second is performing a subtract, and the third is doing a shift.

Is this exactly what it's doing? Not quite, since IA-64 has some enhancements to support parallelism between the cores, but is it "essentially" what's going on? (as I wrote).

Yes.

I don't quite see why these guys are having litters of kittens over this. A triple core CPU is a good thing, or, at least, it would be if the three cores were programmable by a known instruction set.

Imagine what great shape Intel would be in if they'd just done 3 X86-64 (Yamhill) cores!

Instead, they're stuck with this lemon.