ERI Overview and Structure In June 2017, DARPA announced the Electronics Resurgence Initiative (ERI) as a response to several technical and economic trends in the microelectronics sector. Among these trends, the rapid increase in the cost and complexity of advanced microelectronics design and manufacture is challenging a half-century of progress under Moore’s Law, prompting a need for alternative approaches to traditional transistor scaling.
Photonics in the Package for Extreme Scalability (PIPES)
Advances in digital microelectronics have enabled indispensable capabilities for the Department of Defense (DoD) in the fields of information processing, sensors, and communications. Increasingly, system performance in these domains is constrained not by the limits of computation at individual nodes, but by electrical data movement between individual chips.
The Photonics in the Package for Extreme Scalability (PIPES) program is using light to vastly improve the digital connectivity of packaged integrated circuits, with a goal of enabling revolutionary performance gains through parallelism and modularity. PIPES seeks to embed optical signaling technologies within the package of application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) to enable data links with unprecedented bandwidth density, efficiency, and reach. Specifically, PIPES aims to integrate state-of-the-art electronics with photonic modules that deliver 100 Tbps per package at energies less than 1 picojoule per bit, while creating technologies capable of 10x higher performance for future applications.
As PIPES technologies mature, DARPA anticipates pervasive adoption of embedded optics for signaling in advanced microelectronic systems. Beyond FPGAs and specialty DoD products, photonic connectivity for central processing units (CPUs), graphical processing units (GPUs), and domain-specific accelerators will impact a host of dual-use applications, including artificial intelligence, machine learning, large scale emulation, and high performance computing.