Re: I still speculate that AMD works with SUN on their proximity connectivity to speed up communication between chips (Intel's technology is for in between several dies in a single chip). AMD can also use older techniques (wires) to link dies in a chip like Intel is about to use for Core 2 Quad (two Core2 dies in a single chip). Intel's new technique should have vast latency and bandwidth benefits, and might only be limited by how much dies can be fitted in a single chip. I like Intel's approach.
Both Intel's and AMD's approaches are far out technologies, and we may not see them in mass production until the end of the decade. It's like Z-RAM, which everyone expected to see on the roadmaps as soon as the technology was announced. But in reality, it takes a long time to optimize the process for yields (yes, even TSVs need a certain amount of process support to yield well), as well as costs, and get a design in the pipeline that can take advantage of these optimizations (a quad ported cache necessary for optimal sharing among quad cores is extremely difficult to design, let alone caches for greater numbers of cores, so there is a question of how the connection will be made).
But having said all this, I think Intel's stacked memory technique is potentially very beneficial, but probably more so in server workloads and less so in client workloads. I think we are approaching diminishing returns past 4M of cache on the client, but server apps tend to eat up even all the cache a 26.5M Montecito can throw at them. A 256M cache could be enormously beneficial in some workloads, less so in others.
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