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Re: wbmw post# 76275

Friday, 09/29/2006 6:46:26 AM

Friday, September 29, 2006 6:46:26 AM

Post# of 97546
Wbmw, agree. Your rev H thoughts are a bit more detailed than my own where it concerns frequencies - tx.

Just posted this on SI: Intel to marry processor to memory (Through Silicon Vias / TSV): http://news.cnet.co.uk/desktops/0,39029662,49283968,00.htm

It mentions marrying the 80 core prototype chip to 256MB memory (prototype would be marketed in some five years from now). Interesting idea to reduce latency / increase bandwidth.

The article mentions they'll use the same technique for other things. Maybe they mean cpu to cpu.

Meanwhile I still speculate that AMD works with SUN on their proximity connectivity to speed up communication between chips (Intel's technology is for in between several dies in a single chip). AMD can also use older techniques (wires) to link dies in a chip like Intel is about to use for Core 2 Quad (two Core2 dies in a single chip). Intel's new technique should have vast latency and bandwidth benefits, and might only be limited by how much dies can be fitted in a single chip. I like Intel's approach.

Regards,

Rink

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