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borusa

08/06/03 11:27 AM

#10590 RE: SemiconEng #10574

SemiconEng, My sarcasm was in response to yours.

As far as larger wafers, the larger size is obviously causing some cost. What parameter drives this added cost. What might be the trade offs.

I would suggest that in a perfect world Intel would get wafers that matched their specfications. My guess is that when Intel processes a wafer defects are not exclusively random. I can further speculate that the ratio of yeild to wafer size is not liniar.