The FinFET transistor structure vs planar is completely orthogonal to the dimensional scaling that's sort of meant by these names.
The "naming" that Intel uses for example is meant to loosely approximate the scaling in the linear dimension from one node to the next.
So, example:
32nm -> 22nm represented a ~0.5x area reduction. (22nm x 22nm)/(32nm x 32nm) ~= 0.48.
However, there have been times in the past when Intel (and others) have named their nodes in a manner to suggest the 2x area scalling when in fact that was NOT the case.
Take, for example, Intel's 65nm -> 45nm transition. The 45nm SRAMs were about 61% of the area of the 65nm SRAMs, not quite a "full" shrink even though the names suggested such [(45)^2/(65)^2) ~= 0.48).
Intel got away with this because they introduced some nifty new materials science stuff at 45nm compared to 65nm, so even if the shrink wasn't a "full" shrink, they got a very nice transistor performance boost.
The foundries are now doing sort of the same thing, their 20nm -> 14/16nm transition brought no change in gate/metal pitches, but the transistor structure completely changed (planar xtor -> FinFET xtor), giving them a huge performance boost.
The 14/16nm to 10nm transition for TSMC is an honest-to-goodness 50% area reduction, while for Samsung they are claiming a ~30% area reduction (not quite a full shrink).
In going from 10nm -> 7nm, TSMC is claiming a 1.63x-ish improvement in gate density so not quite the 2x improvement in density gen-on-gen that you would expect from the naming.
Intel got honest-to-goodness ~50% area reductions in going from 45nm -> 32nm, from 32nm -> 22nm, and from 22nm -> 14nm, and they say they're getting another one at 10nm. But it is taking them longer to migrate from 14nm -> 10nm than it is for the foundries to go from their 14/16nm to their 10nm, and TSMC is doing another fairly quick jump to 7nm.
Anyway, it's important to keep in mind that area reduction is mainly about cost...transistor/interconnect performance/power consumption is extremely important, too.
Historically, Intel has not led in area but they have had the best transistors/performance (IBM has also been very good here, but they had tremendous difficulties with yields/cost structure).
Intel "took the lead" with its 14nm in terms of density compared to the foundries, but the company's struggles with getting 10nm to ramp is allowing the foundries to regain ground, especially TSMC.
Intel also says it'll stick to 10nm for a while, doing a 10nm, 10nm+, and 10nm++...this suggests that they don't plan to shrink again for a while but do plan to improve the performance of the process. Improved process performance should mean better products in the marketplace.
I hope this helps a bit.
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