Intel Corp (INTC)

[Elmer Phud]

TCaE

Thank you for the explanation, this starts to make some sense. So to restate, you are saying that seeing that even though we no longer have planar transistors, we're accustom to describing process generations in terms of transistor channel dimensions. So if we can scale down the transistor density of a process generation by the equivalent ratio(0.7x), we should be able to call it 10nm because that's what it would be if we were still on planar transistors, even though there is no actual dimension that measures 10nm with FinFets, or is there? FinFets are tapered so where should such a measurement be made?

Additionally, what information do we have on the scaling factor from the foundries when going from 14nm to 10nm? Is it 0.7x?