What I really dont understand is that yield models "for final wafer sorts" do not take the number of metallic layers into consideration: I can hardly imagine defects on and between these layers would be completely irrelevant. Could you (or somebody else) could elaborate on this? (Is this implicitely in different defect densities for different numbers of layers?)
The Dual Damascene Cu Process uses a different technique than the previous Aluminum Process. In Aluminum, the entire wafer was Sputter Depositioned with a layer of metal, then the areas that were not required to have metal traces were etched away. This had a tendency to create the potential of increased particulate matter at the metal layers. In the Cu Process, the standard technique is to "Flow" the liquid Cu in trenches to ceate the traces, and therefore lessens the Metal Layer Particulate present.
Particulate Defects also generally have less of an impact on the Back End metal layers, due to the small size of the Via's, and since there is extensive Wet Cleaning of the Via's and Contacts between each metal layer, prior to the formation of the Metal Layer Interconnects.
Also, generally, a particle landing on the surface of a metal trace, is much less of an issue than a particle landing for example, on the source/drain junction on the front end. After the Via's are formed, a particle would need to be extreamly unlucky to "fall into the via", and in any case, would most likely be cleaned out by the Wet Clean, prior to the via being filled with the interconnect.
The main defect issue on the back end is actually VIA formation, Trench Formation, and Native Oxide regrowth. Particulate Defects probably come out somewhere in the top 5, but I'm not sure I would say top 3.
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