Advanced Micro Devices Inc (AMD)

[kpf]

elmer

Thanks for taking your time to explain.

What I meant by "Timna" approach is Memory Controller and grafics on CPU-die: Two Dothan successor cores with large caches plus memory controller plus grafics. The chipset for it would be Twin Castle (nomen es omen). I dont see a reason this could not be made working in SMP, the basis for Dothan (PIII) works perfectly in dual configurations.

What I really dont understand is that yield models "for final wafer sorts" do not take the number of metallic layers into consideration: I can hardly imagine defects on and between these layers would be completely irrelevant. Could you (or somebody else) could elaborate on this? (Is this implicitely in different defect densities for different numbers of layers?)

As for the capacities - from the list of Intel FABs it is sort of hard to extract waferstarts for CPUs. On the AMD-side that is very easy. Then, again something hard to imagine for me is that Intel would have 100% better CPU-yields than AMD today.
(exactly this thesis some analyst confronted Jerry to last year in May. At this time and for 130nm process in retrospective I think it was accurate.) But now, with an obviously healthy process in Dresden, the numbers of CPUs sold and inventories versus waferstarts and diesizes result in only 60 of yield-figures than your estimates, even taking technology migrations into account allowing only a 75% utilization for volume production.

Somebody could fill this gap between my ears?

K.