elmer
Well, based on "Dual-Timna" products (2cores, big cache(s?), graphics and memory controller on die and the fact "world class yields" are much lower than in the past (because process changes accelerate) an output of 10 Million CPU per quarter and FAB is probably closer than your 40 Mio figure. 200mm facilities could be used for Chipsets or other products or Flash or for possible demand increases or market share gains. If the latter wont occur some of them would have to be closed or sold after the old legacy fabs.
About the yield thing. Could you correct me in the following?
Based on Defect density, Wafer size, edge exclusion and yield model the resulting figure is line yield for one layer, right?
Now, defects in the metallic via-layers and in their connections to the silicon layer have to be taken into consideration as well, right? Plus everything that can go wrong in the backend, right? I am asking that because for the past and present Intel capacities yields as you assume for your 475 GDPW would allow to manufacture a whole lot more CPUs than they sell at full utilization.
K.
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