kpf - Well, based on "Dual-Timna" products (2cores, big cache(s?), graphics and memory controller on die and the fact "world class yields" are much lower than in the past (because process changes accelerate) an output of 10 Million CPU per quarter and FAB is probably closer than your 40 Mio figure. 200mm facilities could be used for Chipsets or other products or Flash or for possible demand increases or market share gains. If the latter wont occur some of them would have to be closed or sold after the old legacy fabs.
Timna had no FSB. This type of chip wouldn't work in a SMP system without some interprocessor connection and Intel likes to design their uPs to be flexable enough to work in single or multiple CPU systems. As for "world class yields" being lower than in the past, all I can say is that someone has given you bad information. I will stick by my estimate assuming the rumors of a ~104mm2 Prescott are correct and Intel has good yields.
About the yield thing. Could you correct me in the following? Based on Defect density, Wafer size, edge exclusion and yield model the resulting figure is line yield for one layer, right?
No, it's the final yield at wafer sort. Pay no attention to the term "line yield". It's just the number of wafers that get broken or otherwise damaged. It has nothing to do with what we think of as yield and the only time I have ever seen it used in a public statement was when the speaker wanted to mislead the audience.
Now, defects in the metallic via-layers and in their connections to the silicon layer have to be taken into consideration as well, right?
I am not a process expert, my field is Test and Design for Test. Experience has shown me that for a production worthy process the yield loss is dominated by particles unless, for marketing reasons, some extraordinary steps are being taken to increase frequency, usually at lithography. Design layouts must conform to design rules which are determined by what the process people can repeatedly and reliably control in HVM. If there are nagging problems with a process step then the process or the design rules (or both) need to be fixed.
Plus everything that can go wrong in the backend, right?
Backend yield should be in the mid to high 90% range mostly due to assemble problems. Little effect here on capacity.
I am asking that because for the past and present Intel capacities yields as you assume for your 475 GDPW would allow to manufacture a whole lot more CPUs than they sell at full utilization.
There is a poster, no names needed, who used to continuously make this argument. However it's not true. Intel is far and away the largest chipset supplier so for each processor they sell they need at least 2 chipset components. If they sell 150 million uPs a year they need somewhere between 250-300 million other support chips. Then you add in StrongArm, Automotive, other uControllers, Ethernet, Cell phone, other Wireless, other Networking, XBox plus they're the largest Flash supplier.
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