Replies to post #9798 on Advanced Micro Devices Inc (AMD)

[Elmer Phud]

kpf - dont think it is an anticipation but a strategy to outproduce competition using its capital and expected 300mm cost advantages. Not sure how exactly they intend to do that. Doubling cache sizes every year is not sufficient to explain the capacities they are building up.

Let's look at that capacity: The most common estimate I see for Prescott is a little over 100mm2. If Intel has very good yields (that's if) then they would get around 475 good Prescott die from each 300mm wafer. If a large fab has a capacity of 6000 WSPW then they could produce nearly 40 million per quarter from each 300mm Fab! I count the following 300mm fabs that will be operational by end of next year when Prescott is fully ramped: F11X, F12, D1C(with a new name), Ireland (with a new name). So if one 300mm Fab could theoretically supply most of the uP requirements, what are the other 3 Mega Fabs for? And this doesn't even include the other large 200mm fabs, F11, F17, F18, F20, F22, IFO etc, not to mention the Flash Fabs and old legacy Fab(s).

What are they thinking? I'd love to be a fly on the wall at one of Intel's long term forecasting meetings!

[Dan3]

Re: What is Intel thinking?

Well, they were thinking they could keep power usage down without SOI.

As it stands, much of that capacity looks useless, since chips large enough to make good use of all that bulk silicon capacity (as opposed to SOI capacity) would dissipate too much heat.

OOOPS!!