Replies to post #142753 on Intel Corp (INTC)

[mas]

Skylake is 5-wide and if there is a hit in the uOp cache it is effectively 6-wide.

http://pc.watch.impress.co.jp/video/pcw/docs/724/408/p01.pdf

Interesting useful info, tnx. More here ...

http://www.anandtech.com/show/9582/intel-skylake-mobile-desktop-launch-architecture-analysis/5

With the micro-ops, Intel has upgraded the front end of the IA core to allow a dispatch of six micro-ops at once, up from four on Haswell. This allows the queue to be quicker, but also the dispatch of micro-ops from the queue to the execution units has increased to six also. Note that the execution units are limited by the number of INT/FP/Load/Store available, so it is the job of the queue to reorder the micro-ops to take advantage of this, as well as manage the memory accesses.

[chipguy]

I would like to see even larger distinction between the server cores and the client Core processors

I don't the core usage model split is as simple as client vs server.

See my previous post.

IMO the more natural split is:

high frequency/power per core:
- desktop, workstation, mobile workstation/desktop replacement laptop,
HPC servers

moderate frequency/power per core:
- phone, tablet, mainstream laptop, scale-out servers, commercial servers

The cores should be very similar in uarch, perhaps logically different
only in FP SIMD execution width. The key difference is the target power
and frequency range driving circuit design and optimization.