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Re: This Causes an Error post# 142753

Wednesday, 11/04/2015 8:04:56 AM

Wednesday, November 04, 2015 8:04:56 AM

Post# of 151655

Skylake is 5-wide and if there is a hit in the uOp cache it is effectively 6-wide.

http://pc.watch.impress.co.jp/video/pcw/docs/724/408/p01.pdf



Interesting useful info, tnx. More here ...

http://www.anandtech.com/show/9582/intel-skylake-mobile-desktop-launch-architecture-analysis/5

With the micro-ops, Intel has upgraded the front end of the IA core to allow a dispatch of six micro-ops at once, up from four on Haswell. This allows the queue to be quicker, but also the dispatch of micro-ops from the queue to the execution units has increased to six also. Note that the execution units are limited by the number of INT/FP/Load/Store available, so it is the job of the queue to reorder the micro-ops to take advantage of this, as well as manage the memory accesses.
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