Replies to post #7699 on Advanced Micro Devices Inc (AMD)

[chipguy]

That is a totally different situation because I am unconvinced that EPIC is the right
direction for processors. I think that Itanium has more than legacy installations to
overcome, it has to overcome its large instruction size.This means that it has an
oversized execution path and always is burdened with needing to flow more memory
into the execution units when compared to other architectures.)

That's what cache's are for. And they are especially effective for storing code due to
its high spacial and temporal locality and the fact that code working set sizes grow
far more slowly than the size of off-chip and on-chip caches. For the 3 MB McKinley
the ratio of the time the processor is stalled for data fetch compared to waiting for
code fetch is between 12:1 and 50:1. And the dominance of data fetch is even higher
in the 6 MB Madison. So your concern about instruction size hurting performance is
not warranted.