chipguy, yes I agree that is why we have caches. Now, my point is a little more subtle than that - if a given architecture requires twice as much instruction cache as a competing architecture, then it will be permanently cost burdened by that cache requirement at a given generation of manufacturing. Not good when Intel should want to move Itanium to the desktop!
Also, twice the memory bandwidth is required for cache misses. This is not something that can be maintained indefinitely over competing architectures.
I don't think it is good design to expect that your manufacturing will always be a generation ahead of the competition, just to keep on an even playing field.
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