Replies to post #136648 on Intel Corp (INTC)

[Unkwn]

Looking at the first die shot, it doesn't look like there's a massive amount of SRAM. And here is a comparison of A7 vs A8 die shots.

Interesting. If the picture is correct, the CPU got its own cache now. Maybe this was needed to increase the memory bandwidth for GPU intense benchmarks, where the A7's SRAM cache needed to be accessed by CPU and GPU in parallel (suspecting it's a shared cache). A smaller local cache for the CPU can reduce CPU accesses to the larger cache and leave it for the GPU. That could make a smaller piece of CPU code, e.g. while executing graphics benchmarks, completely reside in the CPU cache, giving the full bandwidth to the GPU.

Those mobile SoCs start to become really complex. A good piece of logic to best control the handling of those caches is nontrivial.

Anyway, considering the shrink factor of TSMC's 20nm process compared to its 28nm process, it seems that the A7 already must have close to the same amount of transistors as the A8 does (area is already > 10% smaller). Maybe the additional cache brought it above the 2 billion stated.

I don't trust the marked regions in the pictures though. It's hard for me to believe that the CPUs together with the GPUs and their large caches only use about half of the given die area. What would the remaining regions consist of?

Performance wise, A8 is kind of a disappointment I'd say. Kind of supports my thesis that from here, things have to be learned the (very) hard way. Homerun for Intel I'd say.

At least Apple leaves it to the others to simply throw more cores at the problem ...

[chipguy]

Hard to tell from the top metal layer view. Keep in mind SRAM
is about an order of magnitude more transistor dense than
unstructured logic circuitry so it doesn't need a lot of die area
to represent a large portion of the transistor count.