chipguy: Re: Watt-seconds, or more properly, Joules, are units of energy, not instantaneous power draw. I would have thought a self-proclaimed PhD in physics would appreciate the difference between power and energy.
Oh please. Quit trying to nail me on a technicality. I was not talking about *instantaneous* power draw. I was talking about power draw over a period of time - namely 10 clock cycles. You are trying to muddy my point with this inane ruse. I also noticed that you made another feeble attempt at a sideways insult. My Ph.D. is not self-proclaimed, but rather is proclaimed by the Georgia Institute of Technology. Though, I suppose that there is no way for me to prove that, and for that matter, there is no way for me to know that you are an EE. However, your previous claim that the power supply must be designed to manager power surges that last 1 to 10 clock cycles makes me wonder if you got your EE on the internet.
A VRM can't respond in 10 clock cycles as you said, that's what decoupling capacitors are for.
Hmmm. Well, that's not what you said initially. But if you want to change your story, well, then OK. But, remember that your argument was that the *power supply* must be able to meet these 1 to 10 clock cycle power demands. However, I doubt that decaps can dump current that quickly either, but I don't know for sure. At any rate, this is not what decoupling capacitors are for. It may well be an ancillary function to fill in the power gaps created by transients, but the primary function of decaps is to isolate the device from the power bus noise.
Your 99W figure does not represent the maximum thermal load a P4 can draw if it didn't throttle.
It is not *my* figure. It comes directly from the Intel published loadline. I guess that we will just have to disagree on this point. My interpretation of a loadline is something that describes the power envelope of the device, both static and transient. I think that it is clear that 99W is the maximum thermal load the P4 can draw. I think that it is also clear that this would be a transient load. We seem to only disagree on the likely duration of that transient.
Quite a few critics of Intel's TDP numbers like to ignore them and multiply Icc_max and Vcc_max and present that as P4 maximum power from a thermal burden perspective. You happened to be the unlucky person I chose to clarify this point with.
I am frankly not quite sure why you chose me, and I am even more confused about which point you are trying to clarify. I never stated that max power would be obtained by multiplying Icc_max and Vcc_max. In fact, I pointed out (several times, I might add) that this supposition is in fact incorrect. My version of maximum power comes directly from the loadline, on which there is never a possibility of Vcc_max and Icc_max occurring at the same time. Please do not make me state that again.
You have found a second flaw in this approach (ie. the load line) and I thank you for providing me even more ammunition to debunk this myth.
So, then, it is your contention that the loadline is flawed and is a myth? I don't get it. Why would Intel publish such flawed data? Why are you the only one who has discovered this flaw? I suggest that you inform Intel of the error of their ways immediately. I look forward to the datasheet revision that reflects your discovery.
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