I would argue that if it is in the DC Specifications section, then
Icc_max is probably defined as a DC characteristic.
There is no AC section. Besides the loadline is described as including transient limits.
Incidentally, 99 Watts for 10 clock cycles represents an instantaneous power draw of
about 3E-07W-s, or 0.003 milliWatt-seconds. There is no way that this would even be
considered in power supply design.
Watt-seconds, or more properly, Joules, are units of energy, not instantaneous power
draw. I would have thought a self-proclaimed PhD in physics would appreciate the
difference between power and energy.
The critical factors for an uP power supply are its impedance and response to transients,
i.e. not deviating outside the target voltage limits in response to a maximal di/dt event. A
VRM can't respond in 10 clock cycles as you said, that's what decoupling capacitors are
for. And the amount and nature of the decoupling capacitance is always considered as
part of an active power supply design since it affects transient response and even loop
stability.
Despite your penchant for framing my argument for me, I never claimed that maximum
power *should* be considered in thermal design.
Good, that was the point I was trying to bring out. Your 99W figure does not represent the
maximum thermal load a P4 can draw if it didn't throttle. Quite a few critics of Intel's TDP
numbers like to ignore them and multiply Icc_max and Vcc_max and present that as
P4 maximum power from a thermal burden perspective. You happened to be the unlucky
person I chose to clarify this point with. You have found a second flaw in this approach
(ie. the load line) and I thank you for providing me even more ammunition to debunk this
myth.
I think that it is implicit that actual maximum power dissipation is transient in nature and
would be sufficiently absorbed by the thermal inertia of die, heat spreader and cooling
solution in most cases. However, I feel quite certain that transient power peaks driven by
the maximum load as defined in the loadline would significantly exceed 10 clock cycles.
I think it is hard to argue that the instanteous maximum current draw can occur when the
P4 is not issuing the maximum 6 uops per cycle through the six dispatch ports. This can
only occur for a short time since the front end can only fetch 3 uops per cycle (actually 6
uops every other cycle but that isn't relevent here) and the back end can only retire 3 uops
per cycle. So we have a simple queueing problem. The P4 has a uop buffer that can be filled
at a rate of 3 uops per cycle and can be drained at up to 6 uops per cycle. I don't know if
Intel has ever disclosed the uop buffer capacity in either WIllamette or Northwood but it
is likely less, possible far less, than a hundred entries. So under the best possible
circumstances the P4 can issue at 6 uops per cycle (hence drawing Icc_max) for only
a few tens of cycles before the buffer drains and the core is limited by the front end to
3 uops per cycle and less than Icc_max draw.
