Replies to post #5053 on Advanced Micro Devices Inc (AMD)

[spokeshave]

chipguy: Re: The value of Vcc is immaterial to my argument.

Then you should have left it out of your argument. You were arguing against sustaining max power that corresponded to Icc_max and Vcc_max. I was trying, apparently unsuccessfully, to point out that Vcc_max and Icc_max cannot occur at the same time.

The part may draw Icc_max for 1 or even 10 clock cycles
(and the power supply has to be able to handle the instaneous draw)...Icc_max is not a DC value.

Are you sure about this? After all, the loadline and table are included in the Processor DC Specifications section of the datasheet. I would argue that if it is in the DC Specifications section, then Icc_max is probably defined as a DC characteristic.

Incidentally, 99 Watts for 10 clock cycles represents an instantaneous power draw of about 3E-07W-s, or 0.003 milliWatt-seconds. There is no way that this would even be considered in power supply design. It is so minuscule as to be completely and utterly insignificant. Furthermore, I seriously doubt that the VRs could change the voltage or that the caps could dump any significant current in such a short time frame. Each has an internal time constant that probably far exceeds the 3 nanoseconds or so that 10 clock cycles take. Your argument that the power supply must be designed to handle this draw makes no sense at all.

...from the point of considering the thermal design maximum power in the absence of throttling the maximum power will be less than 99 W.

Despite your penchant for framing my argument for me, I never claimed that maximum power *should* be considered in thermal design. I think that it is implicit that actual maximum power dissipation is transient in nature and would be sufficiently absorbed by the thermal inertia of die, heat spreader and cooling solution in most cases. However, I feel quite certain that transient power peaks driven by the maximum load as defined in the loadline would significantly exceed 10 clock cycles.

The entire point of my argument, stated yet again, is that the figures for "maximum" current and voltage given in table 2-6 of the datasheet are not true maximums. This is clearly stated by the footnote. To find true maximums, both static and transient, one must consult the loadline chart and table.

[Petz]

Spoke... gave some good reasons why Iccmax does not occur for periods as short as you imply (you said 1 or 10 clock cycles).

A better reason is that the VRM spec for P4s says that the power supply must "droop" the voltage to the Vccmin level when a current draw equal to Iccmax occurs.

This obviously CAN'T be done in a nanosecond or even a microsecond, because there are capacitors at the output of the supply. Even a millisecond would be tough to accomplish. The time constant of the droop function determines how long Iccmax must occur. If Iccmax never lasted that long, why specify it, since the supply would not be able to droop the voltage output fast enough to meet spec anyway?

Petz

[Petz]

Now, here is a much more relevant question - Why does the P4 3.06/533 and the P4 3.00/800 thermal design power increase by 19% (compared to 2.8/533 and 2.8/800) with only a 7-10% increase in clock frequency and less than 1% increase in supply voltage (Vccmin+Vccmax)/2, not Vid.
(see the table at http://www.investorshub.com/boards/read_msg.asp?message_id=1030357 )

The only way this is possible is if the 3GHZ+ CPUs have specific process or layout changes to increase transistor currents.

Petz