Replies to post #4702 on Advanced Micro Devices Inc (AMD)

[chipguy]

No it hasn't. You think AMD lives in another universe where defects don't happen?

AMD was clever enough to use a delicate package so users will assume
their dead/malfunctioning Athlon was their own fault. Affected users don't
want to appear too stupid to correctly install a heatsink so instead of
complaining on DIY sites they silently go out and buy a new processor.

[Dan3]

Re: This is another testing issue, or test escape.

The curious thing is that, as an in-order processor, I would have thought that Itanium would have been more straightforward to test. Intel spent plenty of time working to validate the chip, and Intel certainly has many, many, many, excellent engineers, so how the heck did this happen? And I don't mean that as a slight against anyone at Intel, it's just very surprising and quite unsettling. I mean, if it could happen with Itanium, it can probably happen with anything.

Perhaps the unusual nature of the Itanium instruction set will take time to learn how to properly test. It still seems like it shouldn't have been such a problem.

[Dan3]

The combination of cycles needed to even condition the part so some obscure internal state can be established and observed exceeds the memory capacity of even the most expensive test systems after only a few milliseconds of actual functional device operation. To test every possible speedpath is impossible even under lab conditions and certainly hopeless in a production environment

But both P4 and Athlon seem to be quite "testable."

[sgolds]

Elmer, I interpreted Intel's guidance that a 'small number of systems' will be affected to mean that only a small number of systems will run under the conditions which will trigger the problem. However, Intel has not given details on what will cause the problem - it is all a little murky. So, is it a binning problem, as you think? Or is it a layout problem that impacts all processors, but only a few will encounter the combination to be affected by the problem? Is it a piece of logic which is inherently difficult to design under the EPIC philosophy?

I don't think you have the answer because Intel hasn't said.

Until Intel specifies the conditions (software, environment, etc.) which will reproduce the problem, and the underlying cause, there really isn't a good way to understand the impact.

That is the other shoe.