Advanced Micro Devices Inc (AMD)

[sgolds]

Elmer, I interpreted Intel's guidance that a 'small number of systems' will be affected to mean that only a small number of systems will run under the conditions which will trigger the problem. However, Intel has not given details on what will cause the problem - it is all a little murky. So, is it a binning problem, as you think? Or is it a layout problem that impacts all processors, but only a few will encounter the combination to be affected by the problem? Is it a piece of logic which is inherently difficult to design under the EPIC philosophy?

I don't think you have the answer because Intel hasn't said.

Until Intel specifies the conditions (software, environment, etc.) which will reproduce the problem, and the underlying cause, there really isn't a good way to understand the impact.

That is the other shoe.