Advanced Micro Devices Inc (AMD)

[wbmw]

YB, Re: The crc vs. ecc in aHT is ok. Remember, ecc is used to control the memory bus, where bits are coming from memory chips, where erros are possible. I'm sure Opteron supports ecc in its memory controller.

ECC and CRC are essentially two ways of performing the same task. They are not mutually exclusive, either. Hypertransport takes data and encodes it into packets, which are transfered over high speed lines. The CRC is encoded as part of the packet, but it typically appears at the end. Thus, the entire packet must be transferred before the hardware knows whether there is an error. I assume errors are then retried on the bus, which may require the suspension of other transactions.

ECC, meanwhile, is transferred along with the data as it is encoded in the packet. The ECC will determine whether the data in the packet is free from errors, rather than the packet itself. Since AMD does not have this, they are risking some reliability issues, but that shouldn't impact anything but mission critical applications. In those cases, they may need to update the protocol to accommodate the higher reliability ratings.

In any case, Elmer's point about CRC eating into performance is a valid one, but I don't see any way to avoid it. High speed transfers are more prone to data than traditional protocols, so you have to update your detection algorithm along with it. CRC is simply the most convenient method to use right now.