Advanced Micro Devices Inc (AMD)

[chipguy]

In cache, there is no commutation within a row as each bit has a different purpose and there is no commutation within the number of cache lines constituting a set. If the cache is 16 way and there are 4 ways a row, then a set is four rows. Lose a column of DRAM and you may fix the array. Lose a column of cache and the whole cache array is shot. Lastly, DRAM has thousands of arrays, cache only has a few.

You are completely clueless about SRAM redundancy. Standard
techniques are common to SRAM and DRAM and have very similar
effectiveness.

Lastly, Intel seems to have either 1or 2 cache arrays for desktops and 2 or 3 arrays for Itanium.

You are even more clueless about IPF cache design. The Madison
9M's L3 is organized into 210 sub-arrays and the Montecito's
cache is organized into 840 sub-arrays. Repair is accomplished
with sub-block replacement, a more powerful technique than row
and column based methods.