Of what, basic chip engineering and economics? Go compare
the die size vs ASP of DRAM versus MPUs. DRAM can sell
for such a remarkably low price compared to die size in large
part due to redundancy and repair. Someone who says an
IPF MPU has a large die size *therefore* it must be really
costly to make is simply ignorant.
DRAM is inherently simpler than cache, for three dozen logic transistors, you have 512 data transistors and 512 capacitors. And adding a few more arrays is easy. Cache has 5 to 10 times the logic inside of DRAM. And although only one stuck transistor out of the half million elements in the DRAM array can stop redundency of spare arrays, a few thousand can stop the redundency of spare cache. Next having extra rows and/or columns in a DRAM array is straight forward and easy due to the strong commutation of bits within an array both vertically and horizontally. In cache, there is no commutation within a row as each bit has a different purpose and there is no commutation within the number of cache lines constituting a set. If the cache is 16 way and there are 4 ways a row, then a set is four rows. Lose a column of DRAM and you may fix the array. Lose a column of cache and the whole cache array is shot. Lastly, DRAM has thousands of arrays, cache only has a few.
So logic is nearly unfixable, but a defect can fall in an area or in such a way that won't affect logic. A rule of thumb is that 70-90% of logic is unfixable when a defect falls within its area. Cache area is like 5-10% unfixable and about 20-30% is fixable by shutting it off. DRAM is less than 1% unfixable and 1-2% by shutting it off. And as the area goes up, DRAM remains with a small chance it is unfixable (that area where it stops redundency of arrays), but cache has an increasing likelyhood that a defect gets into the unfixable area.
So when cache area is much larger than logic, defects in the cache area can scrub the entire chip or force the chip to have only a fraction of its cache. Say if cache is 10 times the logic area, then the die may be unfixable as if the die had 1.5 to 2 times the logic. And there is exists a decent chance that all cache arrays have a shutdown defect in them, so the die is unusable. Lastly, Intel seems to have either 1or 2 cache arrays for desktops and 2 or 3 arrays for Itanium. AMD looks to have at least 4 and as many as 18 cache arrays per die (that may be one reason why AMD has low cache density.
That's quite funny. I look at IPF's primary MPU competitors,
POWER5x and US-IV+, and see external caches of 36 MB
and 32 MB respectively. OTOH IPF systems don't have cache
beyond what is on the MPU. That represents a huge saving
in package pin count/internal routing, signalling power, and
system level physical design complexity for IPF systems.
External caches may simply be SRAM which has commutativity in both directions and thus be highly fixable (the cache logic is on the CPU die) making it high yield and thus, low cost relatively.
Pete
AI
