Advanced Micro Devices Inc (AMD)

[chipguy]

Maybe, but your level of denial is extraordinary.

Of what, basic chip engineering and economics? Go compare
the die size vs ASP of DRAM versus MPUs. DRAM can sell
for such a remarkably low price compared to die size in large
part due to redundancy and repair. Someone who says an
IPF MPU has a large die size *therefore* it must be really
costly to make is simply ignorant.

Are you claiming that Intel knew all along that they'd need humongous cache to make up for the Itanic core's miserable perfomance?

That's quite funny. I look at IPF's primary MPU competitors,
POWER5x and US-IV+, and see external caches of 36 MB
and 32 MB respectively. OTOH IPF systems don't have cache
beyond what is on the MPU. That represents a huge saving
in package pin count/internal routing, signalling power, and
system level physical design complexity for IPF systems.